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720-V/0.35-m<inline-formula> <tex-math notation="LaTeX">$\Omega \cdot$ </tex-math> </inline-formula>cm<sup>2</sup>Fully Vertical GaN-on-Si Power Diodes by Selective Removal of Si Substrates and Buffer Layers
Use of Bilayer Gate Insulator in GaN-on-Si Vertical Trench MOSFETs: Impact on Performance and Reliability
The 14 references without a DOI — listed, not checked
no DOI — not checked1.7 kV/1.0 mOcm2 normally-off vertical GaN transistor on GaN substrate with regrown p-GaN/AlGaN/GaN semipolar gate structure
no DOI — not checked1200V GaN vertical Fin power field-effect transistors
no DOI — not checkedImpact of lowering threading dislocation density on performances of vertical GaN p-n junction diodes
no DOI — not checkedNovel GaN trench MIS barrier Schottky rectifiers with implanted field rings
no DOI — not checked820-V GaN-on-si quasi-vertical p-i-n diodes with BFOM of 2.0 GW/cm2
no DOI — not checkedV. Odnoblyudov et al., U.S. Patent, US10297445B2, May 21, 2019.
no DOI — not checkedFirst demonstration of GaN vertical power FinFETs on engineered substrate
no DOI — not checkedVertical GaN SBDs on large engineered substrates
no DOI — not checkedLateral GaN JFET devices on 200 mm engineered substrates for power switching applications
no DOI — not checkedGrowth of high-quality > 10 µm-thick GaN-on-Si with low-dislocation density in the order of 107/cm2
no DOI — not checked650 V p-GaN gate power HEMTs on 200 mm engineered substrates
no DOI — not checkedDemonstration of high-quality GaN epitaxy on 200mm engineered substrates for vertical power device fabrication
no DOI — not checkedControlled low Si doping and high breakdown voltages in GaN on sapphire grown by MOCVD
no DOI — not checkedRoot cause analysis of gate shorts in semi-vertical GaN MOSFET devices
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