Reference health
Ge<sub>0.95</sub>Sn<sub>0.05</sub> Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width
45/45 checkable references clean · checked 2026-07-24
Every reference with a DOI in the deposited reference list resolved to a known work in Crossref or DataCite at the dated check, and none carried a retraction, withdrawal, or removal notice.
8 without a DOI — not checked. A reference deposited without a DOI is never matched by title or guessed at; it stays outside the checked set, and this line discloses that.
The 45 checked references that resolve
resolves10.1109/IEDM.2007.4418914
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
resolves10.1109/IEDM.2008.4796777
A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&#x03BC;m<sup>2</sup> SRAM cell size in a 291Mb array
resolves10.1109/VLSIT.2012.6242496
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
resolves10.1063/1.3318249
Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire metal-oxide-semiconductor-field-effect-transistors
resolves10.1109/IEDM.2008.4796804
Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration?
resolves10.1109/IEDM.2013.6724699
Asymetrically strained high performance Germanium gate-all-around nanowire p-FETs featuring 3.5 nm wire width and contractible phase change liner stressor (Ge<inf>2</inf>Sb<inf>2</inf>Te<inf>5</inf>)
resolves10.1109/IEDM.2015.7409610
First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters
resolves10.1109/VLSIT.2016.7573416
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
resolves10.23919/VLSIT.2017.7998183
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
resolves10.1016/j.sse.2019.107736
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
resolves10.1109/55.902843
On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?
resolves10.1109/IEDM.2014.7047061
First demonstration of high-Ge-content strained-Si<inf>1&#x2212;x</inf>Ge<inf>x</inf> (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications
resolves10.1109/VLSIT.2018.8510693
GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest G<inf>m,int</inf> of 900 µS/µm, and High-Field µ<inf>eff</inf> of 275 cm<sup>2</sup>/V•s
resolves10.1109/IEDM.2018.8614536
First Transistor Demonstration of Thermal Atomic Layer Etching: InGaAs FinFETs with sub-5 nm Fin-width Featuring in situ ALE-ALD
resolves10.1021/acs.nanolett.9b01525
In Situ Thermal Atomic Layer Etching for Sub-5 nm InGaAs Multigate MOSFETs
resolves10.1109/VLSIT.2012.6242478
GeSn channel nMOSFETs: Material potential and technological outlook
resolves10.1109/LED.2012.2236880
Germanium&#x2013;Tin (GeSn) p-Channel MOSFETs Fabricated on (100) and (111) Surface Orientations With Sub-400 <formula formulatype="inline"><tex Notation="TeX">$^{\circ}\hbox{C}\ \hbox{Si}_{2}\hbox{H}_{6}$</tex> </formula> Passivation
resolves10.1109/IEDM.2015.7409613
Germanium-based transistors for future high performance and low power logic applications
resolves10.23919/VLSIT.2017.7998170
The first GeSn FinFET on a novel GeSnOI substrate achieving lowest S of 79 mV/decade and record high Gm, int of 807 μS/μm for GeSn P-FETs
resolves10.1021/nl203238e
Room-Temperature Quantum Confinement Effects in Transport Properties of Ultrathin Si Nanowire Field-Effect Transistors
resolves10.1021/nl103278a
Quantum Confinement Induced Performance Enhancement in Sub-5-nm Lithographic Si Nanowire Transistors
resolves10.1109/TED.2019.2960269
BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs
resolves10.1109/VLSIT.2018.8510646
Hole mobility enhancement in extremely-thin-body strained GOI and SGOI pMOSFETs by improved Ge condensation method
resolves10.1063/1.4895487
Fabrication and characterization of germanium-on-insulator through epitaxy, bonding, and layer transfer
resolves10.1364/OE.27.005798
High-speed photo detection at two-micron-wavelength: technology enablement by GeSn/Ge multiple-quantum-well photodiode on 300 mm Si substrate
resolves10.1016/j.sse.2009.12.018
Hole transport in DGSOI devices: Orientation and silicon thickness effects
resolves10.1063/1.1358321
Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion
resolves10.1109/VLSI-TSA.2019.8804647
The First GeSn Gate-All-Around Nanowire P-FET on the GeSnOI Substrate with Channel Length of 20 nm and Subthreshold Swing of 74 mV/decade
resolves10.1109/IEDM19573.2019.8993594
First Stacked Ge<sub>0.88</sub>Sn<sub>0.12</sub> pGAAFETs with Cap, LG=4Onm, Compressive Strain of 3.3%, and High S/D Doping by CVD Epitaxy Featuring Record ION of 58µA at V<sub>OV</sub>=V<sub>DS</sub>= -0.5V, Record G<sub>m,max</sub> of 172µS at V<sub>DS</sub>= -0.5V, and Low Noise
The 8 references without a DOI — listed, not checked
no DOI — not checkedInternational Roadmap for Devices and Systems (IRDS). IEEE, 2020. https://irds.ieee.org/editions/2020.
no DOI — not checkedYeap, G.; Lin, S. S.; Chen, Y. M.; Shang, H. L.; Wang, P. W.; Lin, H. C.; Peng, Y. C.; Sheu, J. Y.; Wang, M.; Chen, X.; 5 nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021 μm2 SRAM cells for Mobile SoC and High Performance Computing Applications. In IEEE International Electron Devices Meeting (IEDM);Dec 7–11, 2019; IEEE: Piscataway, NJ, 2019; pp 879–882.
no DOI — not checkedLee, H.; Yu, L.E.; Ryu, S.W.; Han, J.W.; Jeon, K.; Jang, D.Y.; Kim, K.H.; Lee, J.; Kim, J.H.; Jeon, S. C.; Sub-5 nm All-Around Gate FinFET for Ultimate Scaling. In IEEE Symposium on VLSI Technology;June 13–15, 2006; IEEE: Piscataway, NJ, 2006.
no DOI — not checkedHan, G.; Su, S.; Zhan, C.; Zhou, Q.; Yang, Y.; Wang, L.; Guo, P.; Wang, W.; Wong, C. P.; Shen, Z. X.; High-Mobility Germanium-Tin (GeSn) P-channel MOSFETs Featuring Metallic Source/Drain and Sub-370 °C Process Modules. In IEEE International Electron Devices Meeting (IEDM);Dec 5–7, 2011; IEEE: Piscataway, NJ, 2011; pp 402–404.
no DOI — not checkedHuang, Y.S.; Huang, C.H.; Lu, F.L.; Lin, C.Y.; Ye, H.Y.; Wong, I.H.; Jan, S.R.; Lan, H.S.; Liu, C.W. Record High Mobility (428 cm2/(V s)) of CVD-grown Ge/Strained Ge0.91Sn0.09/Ge Quantum Well p-MOSFETs. In IEEE International Electron Devices Meeting (IEDM);Dec 3–7, 2016; IEEE: Piscataway, NJ, 2016; pp 822–825.
no DOI — not checkedUchida, K.; Watanabe, H.; Kinoshita, A.; Koga, J.; Numata, T.; Takagi, S. Experimental Study on Carrier Transport Mechanism in Ultrathin-body SOI n- and p-MOSFETs with SOI Thickness less than 5 nm. In IEEE International Electron Devices Meeting (IEDM);Dec 8–11, 2002; IEEE: Piscataway, NJ, 2002; pp 47–50.
no DOI — not checkedHuang, Y.S.; Lu, F.L.; Tsou, Y.J.; Tsai, C.E.; Lin, C.Y.; Huang, C.H.; Liu, C. W. First Vertically Stacked GeSn Nanowire pGAAFETs with Ion=1850 μA/μm (VOV=VDS=-1V) on Si by GeSn/Ge CVD Epitaxial Growth and Optimum Selective Etching. In IEEE International Electron Devices Meeting (IEDM);Dec 2–6, 2017; IEEE: Piscataway, NJ, 2017; pp 832–835.
no DOI — not checkedHuang, Y.S.; Ye, H.Y.; Lu, F.L.; Liu, Y.C., Tu, C.T.; Lin, C.Y.; Lin, S.Y.; Jan, S.R.; Liu, C. W. First Vertically Stacked, Compressively Strained, and Triangular Ge0.91Sn0.09 pGAAFETs with High ION of 19.3 μA at VOV=VDS=-0.5V, Gm of 50.2 μS at VDS=-0.5V and Low SSlin of 84 mV/dec by CVD Epitaxy and Orientation Dependent Etching. In IEEE Symposium on VLSI Technology;June 9–14, 2019; IEEE: Piscataway, NJ, 2019; pp T180–T181.
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