Every reference with a DOI in the deposited reference list resolved to a known
work in Crossref or DataCite at the dated check, and none carried a retraction,
withdrawal, or removal notice.
The 50 checked references that resolve
resolves10.1109/TNN.2005.860850A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity
resolves10.1002/adma.200900375Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges
resolves10.1063/1.3319591Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells
resolves10.1523/JNEUROSCI.18-24-10464.1998Synaptic Modifications in Cultured Hippocampal Neurons: Dependence on Spike Timing, Synaptic Strength, and Postsynaptic Cell Type
resolves10.1038/srep04755Enabling an Integrated Rate-temporal Learning Scheme on Memristor
resolves10.1021/nl904092hNanoscale Memristor Device as Synapse in Neuromorphic Systems
resolves10.1002/adma.201503202Memristive Physically Evolving Networks Enabling the Emulation of Heterosynaptic Plasticity
resolves10.1002/adfm.201501427Biorealistic Implementation of Synaptic Functions with Oxide Memristors through Internal Ionic Dynamics
resolves10.1038/srep18639Emulating short-term synaptic dynamics with memristive devices
resolves10.1038/nature14441Training and operation of an integrated neuromorphic network based on metal-oxide memristors
resolves10.3389/fnins.2014.00205Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array
resolves10.1109/TED.2015.2439635Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element
resolves10.1063/1.4749411Physical aspects of low power synapses based on phase change memory devices
resolves10.1109/4.229397A high-precision VLSI winner-take-all circuit for self-organizing neural networks
resolves10.1023/A:1011208127849A Current-Mode Hysteretic Winner-take-all Network, with Excitatory and Inhibitory Coupling
resolves10.1049/el:19930606CMOS current mode winner-take-all circuit with both excitatory and inhibitory feedback
resolves10.1109/TED.2015.2433676A <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-Controller-Based System for Interfacing Selectorless RRAM Crossbar Arrays
resolves10.1038/nmat2748Complementary resistive switches for passive nanocrossbar memories
resolves10.1371/journal.pone.0134356Distributed Bayesian Computation and Self-Organized Learning in Sheets of Spiking Neurons with Local Lateral Inhibition
resolves10.1038/nature01273Long-term in vivo imaging of experience-dependent synaptic plasticity in adult cortex
The 13 references without a DOI — listed, not checked
no DOI — not checkedIndiveri, G. et al. Neuromorphic silicon neuron circuits. Front. Neurosci. 5, 73 (2011).
no DOI — not checkedGovoreanu, B. et al. in Proc. 2011 IEEE International Electron Devices Meeting (ed. Mahoney, P. W.) 31.6 (IEEE, (2011).
no DOI — not checkedGupta, I. et al. Memristive integrative sensors for neuronal activity. Preprint at http://arxiv.org/abs/1507.06832 (2015).
no DOI — not checkedMa, X., Strukov, D. B., Lee, J. H. & Likharev, K. K. in Proc. 5th IEEE Conference on Nanotechnology (ed. Arai, F.) 175–178 (IEEE, (2005).
no DOI — not checkedWei, S. L. et al. Emulating long-term synaptic dynamics with memristive devices. Preprint at http://arxiv.org/abs/1509.01998 (2015).
no DOI — not checkedDu, N. et al. Single pairing spike-timing dependent plasticity in BiFeO3 memristors with a time window of 25 ms to 125 μs. Front. Neurosci. 9, 227 (2015).
no DOI — not checkedMayr, C. et al. in Proc. NIPS 2012 - Advances in Neural Information Processing Systems 25 (ed. Pereira, F. et al.) 1700–1708 (Neural Information Processing Systems Foundation, Inc., 2012).
no DOI — not checkedBill, J. & Legenstein, R. A compound memristive synapse model for statistical learning through STDP in spiking neural networks. Front. Neurosci. 8, 412 (2014).
no DOI — not checkedHabenschuss, S., Bill, J. & Nessler, B. in Proc. NIPS 2012 - Advances in Neural Information Processing Systems 25 (eds Pereira, F. et al.) 773–781 (Neural Information Processing Systems Foundation, Inc., (2012).
no DOI — not checkedNessler, B., Pfeiffer, M. & Maass, W. in Advances in Neural Information Processing Systems, 1357–1365 (2009).
no DOI — not checkedLeung, W., Hsu, F.-C. & Jones, M.-E. in Proc. IEEE International ASIC/SOC Conference (eds Buchner, T. et al.) 32–36 (IEEE, (2000).
no DOI — not checkedBurr, G. W. et al. in Proc. VLSIT 2013 - Symposium on VLSI Technology (ed. Jammy, R.) T66–T67 (IEEE, (2013).
no DOI — not checkedKappel, D., Habenschuss, S., Legenstein, R. & Maass, W. in Advances in Neural Information Processing Systems, 370–378 (2015).
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