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Vertical GaN trench MOSFETs with step-graded channel doping

27/27 checkable references clean · checked 2026-07-23

Every reference with a DOI in the deposited reference list resolved to a known work in Crossref or DataCite at the dated check, and none carried a retraction, withdrawal, or removal notice.

3 without a DOI — not checked. A reference deposited without a DOI is never matched by title or guessed at; it stays outside the checked set, and this line discloses that.

The 27 checked references that resolve

resolves10.1063/5.0061354

GaN-based power devices: Physics, reliability, and perspectives

resolves10.1109/TED.2018.2808345

Characterization of 880 V Normally Off GaN MOSHEMT on Silicon Substrate Fabricated With a Plasma-Free, Self-Terminated Gate Recess Process

resolves10.1109/LED.2017.2749678

Breakdown Enhancement and Current Collapse Suppression by High-Resistivity GaN Cap Layer in Normally-Off AlGaN/GaN HEMTs

resolves10.1109/LED.2018.2792839

Enhancement-Mode GaN MOS-HEMTs With Recess-Free Barrier Engineering and High- ${k}$ ZrO2 Gate Dielectric

resolves10.7567/APEX.8.054101

1.8 mΩ·cm<sup>2</sup>vertical GaN-based trench metal–oxide–semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation

resolves10.1109/LED.2016.2614515

600 V/ $1.7~\Omega$ Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor

resolves10.1109/LED.2021.3080260

Effects of p-GaN Body Doping Concentration on the ON-State Performance of Vertical GaN Trench MOSFETs

resolves10.1109/LED.2017.2779445

GaN-on-Si Quasi-Vertical Power MOSFETs

resolves10.1109/LED.2019.2894177

Fully Vertical GaN-on-Si power MOSFETs

resolves10.1109/LED.2022.3146276

Enhancing ON- and OFF-State Performance of Quasi-Vertical GaN Trench MOSFETs on Sapphire With Reduced Interface Charges and a Thick Bottom Dielectric

resolves10.1109/LED.2016.2616508

OG-FET: An In-Situ ${O}$ xide, ${G}$ aN Interlayer-Based Vertical Trench MOSFET

resolves10.1109/LED.2017.2649599

In Situ <italic>O</italic>xide, <italic>G</italic>aN Interlayer-Based Vertical Trench MOS<italic>FET</italic> (<italic>OG-FET</italic>) on Bulk GaN substrates

resolves10.1109/LED.2018.2813312

Large-Area <italic>In-Situ</italic> Oxide, GaN Interlayer-Based Vertical Trench MOSFET (OG-FET)

resolves10.1109/LED.2014.2339197

1.5-kV and 2.2-m<inline-formula> <tex-math notation="TeX">$\Omega $ </tex-math></inline-formula>-cm<inline-formula> <tex-math notation="TeX">$^{2}$ </tex-math></inline-formula> Vertical GaN Transistors on Bulk-GaN Substrates

resolves10.1109/LED.2017.2670925

High-Performance GaN Vertical Fin Power Transistors on Bulk GaN Substrates

resolves10.1109/LED.2018.2880306

Large Area 1.2 kV GaN Vertical Power FinFETs with a Record Switching Figure-of-Merit

resolves10.1143/APEX.1.021104

GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

resolves10.7567/APEX.9.121001

Comparing electrical performance of GaN trench-gate MOSFETs with a-plane and m-plane sidewall channels

resolves10.35848/1882-0786/abcdbb

Improvement of channel property of GaN vertical trench MOSFET by compensating nitrogen vacancies with nitrogen plasma treatment

resolves10.1063/1.4983558

Trench formation and corner rounding in vertical GaN power devices

resolves10.1063/5.0040920

Formation of highly vertical trenches with rounded corners via inductively coupled plasma reactive ion etching for vertical GaN power devices

resolves10.1109/TED.2010.2057197

Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

resolves10.1109/TED.2002.804697

Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

resolves10.7567/APEX.10.121004

Control of the inversion-channel MOS properties by Mg doping in homoepitaxial p-GaN layers

resolves10.1109/16.563368

Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's

resolves10.1109/16.556154

The threshold-voltage model of MOSFET devices with localized interface charge

resolves10.1109/16.477596

A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFETs

The 3 references without a DOI — listed, not checked

no DOI — not checked2023081001100010600_c13

no DOI — not checked2023081001100010600_c16

no DOI — not checked2023081001100010600_c18

What this badge says. CiteStamped means the CHECKABLE references of this work were clean at the dated check: each resolved to a known work in a public registry, and none carried a retraction notice at that time. It says nothing about the quality, findings, or importance of the work itself, and nothing about references deposited without a DOI.

checked 2026-07-23 — re-checked daily as this page is visited; titles and statuses come from Crossref and DataCite and are not part of the signed record

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