Reference health

Math Doesn't Have to be Hard

https://doi.org/10.1145/3289602.3293912
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14/14 checkable references clean · checked 2026-07-26

Every reference with a DOI in the deposited reference list resolved to a known work in Crossref or DataCite at the dated check, and none carried a retraction, withdrawal, or removal notice.

11 without a DOI — not checked. A reference deposited without a DOI is never matched by title or guessed at; it stays outside the checked set, and this line discloses that.

The 14 checked references that resolve
resolves10.1109/TVLSI.2004.824300
The effect of LUT and cluster size on deep-submicron FPGA performance and density
resolves10.1109/T-C.1973.223648
A Two's Complement Parallel Array Multiplication Algorithm
resolves10.1145/3242898
You Cannot Improve What You Do not Measure
resolves10.1145/2684746.2689077
Enhancements in UltraScale CLB Architecture
resolves10.1109/ISCA.2018.00012
A Configurable Cloud-Scale DNN Processor for Real-Time AI
resolves10.1109/FPT.2006.270384
Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters
resolves10.1109/TVLSI.2009.2031318
Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design
resolves10.1145/2684746.2689071
Floating-Point DSP Block Architecture for FPGAs
resolves10.1145/1046192.1046195
The Stratix II logic and routing architecture
resolves10.1145/2847263.2847267
The Stratix™ 10 Highly Pipelined FPGA Architecture
resolves10.1109/5.231340
Architecture of field-programmable gate arrays
resolves10.1109/JPROC.2017.2761740
Efficient Processing of Deep Neural Networks: A Tutorial and Survey
resolves10.1109/JPROC.2015.2392104
Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology
resolves10.1109/FPT.2017.8280115
Automatic circuit design and modelling for heterogeneous FPGAs
The 11 references without a DOI — listed, not checked
no DOI — not checkedA. Boutros mbox . 2018 a. Embracing diversity: Enhanced DSP blocks for low-precision deep learning on FPGAs. In FPL . 1--8. A. Boutros et almbox. 2018a. Embracing diversity: Enhanced DSP blocks for low-precision deep learning on FPGAs. In FPL . 1--8.
no DOI — not checkedM. Burich . 2012 . Conference workshop: FPGAs in 2032 , challenges and opportunities in the next 20 years, convergence of programmable solutions . In FPGA . M. Burich. 2012. Conference workshop: FPGAs in 2032, challenges and opportunities in the next 20 years, convergence of programmable solutions . In FPGA .
no DOI — not checkedC. Chiasson and V. Betz . 2013 . COFFE: Fully-automated transistor sizing for FPGAs. In FPT. 34--41. C. Chiasson and V. Betz. 2013. COFFE: Fully-automated transistor sizing for FPGAs. In FPT. 34--41.
no DOI — not checkedI. Goodfellow mbox . 2016 . Deep learning. Vol. 1 . MIT press Cambridge . I. Goodfellow et almbox. 2016. Deep learning. Vol. 1. MIT press Cambridge.
no DOI — not checkedIntel Corporation. 2017. Intel Stratix 10 logic array blocks and adaptive logic modules user guide (UG-S10LAB) . Intel Corporation. 2017. Intel Stratix 10 logic array blocks and adaptive logic modules user guide (UG-S10LAB) .
no DOI — not checkedA. Krizhevsky mbox . 2012 . ImageNet classification with deep convolutional neural networks. In NIPS . 1097--1105. A. Krizhevsky et almbox. 2012. ImageNet classification with deep convolutional neural networks. In NIPS . 1097--1105.
no DOI — not checkedJ. Luu mbox . 2014 . On hard adders and carry chains in FPGAs. In FCCM. 52--59. J. Luu et almbox. 2014. On hard adders and carry chains in FPGAs. In FCCM. 52--59.
no DOI — not checkedA. Mishra mbox . 2017 . WRPN : wide reduced-precision networks. arXiv preprint arXiv:1709.01134 . A. Mishra et almbox. 2017. WRPN: wide reduced-precision networks. arXiv preprint arXiv:1709.01134 .
no DOI — not checkedV. Rybalkin mbox . 2018 . FINN-L: Library extensions and design trade-off analysis for variable precision LSTM networks on FPGAs. In FPL . 1--8. V. Rybalkin et almbox. 2018. FINN-L: Library extensions and design trade-off analysis for variable precision LSTM networks on FPGAs. In FPL. 1--8.
no DOI — not checkedXilinx Inc. 2017. Virtex UltraScale Xilinx Inc. 2017. Virtex UltraScale
no DOI — not checkedHBM FPGA: A revolutionary increase in memory performance. HBM FPGA: A revolutionary increase in memory performance.
What this badge says. CiteStamped means the CHECKABLE references of this work were clean at the dated check: each resolved to a known work in a public registry, and none carried a retraction notice at that time. It says nothing about the quality, findings, or importance of the work itself, and nothing about references deposited without a DOI.

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