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Formal system‐level design space exploration

https://doi.org/10.1002/cpe.2802
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-45874-3_2openalex-snapshot
A Methodology to Design Programmable Embedded Systems
inferredcites →https://doi.org/10.1007/978-3-540-73368-3_18openalex-snapshot
CADP 2006: A Toolbox for the Construction and Analysis of Distributed Processes
inferredcites →https://doi.org/10.1007/978-3-642-02571-6_18openalex-snapshot
Fast Simulation Techniques for Design Space Exploration
inferredcites →https://doi.org/10.1007/s11241-006-6884-xopenalex-snapshot
A framework for modular analysis and exploration of heterogeneous embedded systems
inferredcites →https://doi.org/10.1023/a:1012231429554openalex-snapshot
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems
inferredcites →https://doi.org/10.1049/ip-cdt:20045088openalex-snapshot
System level performance analysis – the SymTA/S approach
inferredcites →https://doi.org/10.1109/date.2005.20openalex-snapshot
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
inferredcites →https://doi.org/10.1109/date.2006.244110openalex-snapshot
Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design
inferredcites →https://doi.org/10.1109/date.2008.4484910openalex-snapshot
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs
inferredcites →https://doi.org/10.1109/date.2009.5090645openalex-snapshot
A formal approach to design space exploration of protocol converters
inferredcites →https://doi.org/10.1109/date.2009.5090662openalex-snapshot
A co-design approach for embedded system modeling and code generation with UML and MARTE
inferredcites →https://doi.org/10.1109/dsd.2006.19openalex-snapshot
Abstract Application Modeling for System Design Space Exploration
inferredcites →https://doi.org/10.1109/icecs.2006.379694openalex-snapshot
A UML-based Environment for System Design Space Exploration
inferredcites →https://doi.org/10.1109/ipdps.2006.1639422openalex-snapshot
Timed automata based analysis of embedded system architectures
inferredcites →https://doi.org/10.1109/issoc.2005.1595642openalex-snapshot
Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems
inferredcites →https://doi.org/10.1109/memcod.2003.1210105openalex-snapshot
LOTOS code generation for model checking of STBus based SoC: the STBus interconnection
inferredcites →https://doi.org/10.1109/rsp.2009.27openalex-snapshot
High-Level System Modeling for Rapid HW/SW Architecture Exploration
inferredcites →https://doi.org/10.1109/sccc.2007.17openalex-snapshot
Reducing Component Systems' Behavior Specification
inferredcites →https://doi.org/10.1109/sccc.2007.21openalex-snapshot
Specifying Fractal and GCM Components with UML
inferredcites →https://doi.org/10.1109/tse.2004.1265812openalex-snapshot
IEEE Transactions on Software Engineering
inferredcites →https://doi.org/10.1109/tse.2004.34openalex-snapshot
TURTLE: A Real-Time UML Profile Supported by a Formal Validation Toolkit
inferredcites →https://doi.org/10.1145/1071021.1071022openalex-snapshot
Performance by unified model analysis (PUMA)
inferredcites →https://doi.org/10.1145/1142980.1142983openalex-snapshot
Computation and communication refinement for multiprocessor SoC design
inferredcites →https://doi.org/10.1145/1403375.1403564openalex-snapshot
A mapping framework for guided design space exploration of heterogeneous MP-SoCs
inferredcites →https://doi.org/10.1145/1416729.1416764openalex-snapshot
TTool for DIPLODOCUS
inferredcites →https://doi.org/10.1145/1921532.1921556openalex-snapshot
TEPE
inferredcites →https://doi.org/10.1145/371636.371719openalex-snapshot
High-level architectural co-simulation using Esterel and C
inferredcites →https://doi.org/10.5555/1874620.1874651openalex-snapshot
A formal approach to design space exploration of protocol converters
inferredcites →https://doi.org/10.5555/823453.823850openalex-snapshot
LOTOS code generation for model checking of STBus based SoC: the STBus interconnection

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.2818openalex-snapshot
Special Issue Editorial: New technologies of distributed systems
inferred← citeshttps://doi.org/10.1002/cpe.3857openalex-snapshot
Special issue Editorial: New technologies of distributed systems
inferred← citeshttps://doi.org/10.1007/978-3-319-94764-8_3openalex-snapshot
Formal and Virtual Multi-level Design Space Exploration
inferred← citeshttps://doi.org/10.1007/978-3-642-41947-8_33openalex-snapshot
Behavior Analysis of Real-Time Systems Using PLA Method
inferred← citeshttps://doi.org/10.1007/s10270-026-01388-4openalex-snapshot
On the consistency of state machines, use cases and block diagrams using dependency graphs and Large Language Models
inferred← citeshttps://doi.org/10.1016/j.jss.2013.03.078openalex-snapshot
Efficient optimization of large probabilistic models
inferred← citeshttps://doi.org/10.1109/seaa.2012.36openalex-snapshot
DiplodocusDF, a Domain-Specific Modelling Language for Software Defined Radio Applications
inferred← citeshttps://doi.org/10.1109/seaa.2013.8openalex-snapshot
Fast Evaluation of Power Consumption of Embedded Systems Using DIPLODOCUS
inferred← citeshttps://doi.org/10.1145/3640310.3674079openalex-snapshot
AI-Driven Consistency of SysML Diagrams
inferred← citeshttps://doi.org/10.5220/0006535902950302openalex-snapshot
Multi-level Latency Evaluation with an MDE Approach
inferred← citeshttps://doi.org/10.70675/13d5944bzddb3z4ac7z95d6zd846ae5be8f2openalex-snapshot
Efficient scheduling of applications onto cloud FPGAs
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.