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Execution‐Cache‐Memory modeling and performance tuning of sparse matrix‐vector multiplication and Lattice quantum chromodynamics on A64FX
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-56702-0_1openalex-snapshot
Kerncraft: A Tool for Analytic Performance Modeling of Loop Kernels
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A method for simulating chiral fermions on the lattice
inferredcites →https://doi.org/10.1016/0550-3213(95)00031-mopenalex-snapshot
Axial symmetries in lattice QCD with Kaplan fermions
inferredcites →https://doi.org/10.1016/b978-0-12-803819-2.00023-9openalex-snapshot
Wilson Dslash Kernel From Lattice QCD Optimization
inferredcites →https://doi.org/10.1016/b978-0-444-82849-1.x5000-3openalex-snapshot
Parallel Computational Fluid Dynamics 1997
inferredcites →https://doi.org/10.1016/b978-044482851-4/50030-xopenalex-snapshot
Towards Realistic Performance Bounds for Implicit CFD Codes
inferredcites →https://doi.org/10.1109/cgo51591.2021.9370316openalex-snapshot
YaskSite: Stencil Optimization Techniques Applied to Explicit ODE Methods on Modern Architectures
inferredcites →https://doi.org/10.1109/cluster.2018.00079openalex-snapshot
SVE-Enabling Lattice QCD Codes
inferredcites →https://doi.org/10.1109/cluster49012.2020.00069openalex-snapshot
Evaluation of Power Management Control on the Supercomputer Fugaku
inferredcites →https://doi.org/10.1109/cluster49012.2020.00075openalex-snapshot
Preliminary Performance Evaluation of the Fujitsu A64FX Using HPC Applications
inferredcites →https://doi.org/10.1109/cluster49012.2020.00076openalex-snapshot
The Effects of Wide Vector Operations on Processor Caches
inferredcites →https://doi.org/10.1109/cluster49012.2020.00079openalex-snapshot
Porting Applications to Arm-based Processors
inferredcites →https://doi.org/10.1109/cluster49012.2020.00080openalex-snapshot
Performance Evaluation of ParalleX Execution model on Arm-based Platforms
inferredcites →https://doi.org/10.1109/icppw.2010.38openalex-snapshot
LIKWID: A Lightweight Performance-Oriented Tool Suite for x86 Multicore Environments
inferredcites →https://doi.org/10.1109/mc.2016.308openalex-snapshot
Standardizing Power Monitoring and Control at Exascale
inferredcites →https://doi.org/10.1109/pmbs.2018.8641578openalex-snapshot
Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures
inferredcites →https://doi.org/10.1109/pmbs49563.2019.00006openalex-snapshot
Automatic Throughput and Critical Path Analysis of x86 and ARM Assembly Kernels
inferredcites →https://doi.org/10.1109/pmbs51919.2020.00006openalex-snapshot
Performance Modeling of Streaming Kernels and Sparse Matrix-Vector Multiplication on A64FX
inferredcites →https://doi.org/10.1109/sc.2000.10015openalex-snapshot
Tiling Optimizations for 3D Scientific Computations
inferredcites →https://doi.org/10.1109/sc.2014.11openalex-snapshot
Lattice QCD with Domain Decomposition on Intel® Xeon Phi Co-Processors
inferredcites →https://doi.org/10.1137/130930352openalex-snapshot
A Unified Sparse Matrix Data Format for Efficient General Sparse Matrix-Vector Multiplication on Modern Processors with Wide SIMD Units
inferredcites →https://doi.org/10.1145/2049662.2049663openalex-snapshot
The university of Florida sparse matrix collection
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Quantifying Performance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.14529/jsfi190301openalex-snapshot
Collecting and Presenting Reproducible Intranode Stencil Performance: INSPECT
inferredcites →https://doi.org/10.14529/jsfi200204openalex-snapshot
Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors
inferredcites →https://doi.org/10.22323/1.251.0023openalex-snapshot
Grid: A next generation data parallel C++ QCD library
inferredcites →https://doi.org/10.22323/1.334.0316openalex-snapshot
Lattice QCD on upcoming ARM architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Special issue on Performance modeling, benchmarking, and simulation of high performance computing systems
inferred← citeshttps://doi.org/10.1007/978-3-031-29927-8_35openalex-snapshot
A Profiling-Based Approach to Cache Partitioning of Program Data
inferred← citeshttps://doi.org/10.1007/978-3-031-85697-6_7openalex-snapshot
Introducing the Arm-Membench Throughput Benchmark
inferred← citeshttps://doi.org/10.1007/s42514-023-00160-0openalex-snapshot
Uncovering the performance bottleneck of modern HPC processor with static code analyzer: a case study on Kunpeng 920
inferred← citeshttps://doi.org/10.1016/b978-0-443-45574-2.00017-4openalex-snapshot
OpenMP for multithreading
inferred← citeshttps://doi.org/10.1016/j.future.2023.01.015openalex-snapshot
HPCG on long-vector architectures: Evaluation and optimization on NEC SX-Aurora and RISC-V
inferred← citeshttps://doi.org/10.1016/j.jpdc.2024.104941openalex-snapshot
SpChar: Characterizing the sparse puzzle via decision trees
inferred← citeshttps://doi.org/10.1016/j.parco.2025.103169openalex-snapshot
Cache partitioning for sparse matrix–vector multiplication on the A64FX
inferred← citeshttps://doi.org/10.1016/j.parco.2026.103183openalex-snapshot
Microarchitectural comparison, in-core modeling, and memory hierarchy analysis of state-of-the-art CPUs: Grace, Sapphire Rapids, and Genoa
inferred← citeshttps://doi.org/10.1109/hipc58850.2023.00042openalex-snapshot
Optimizing the Training of Co-Located Deep Learning Models Using Cache-Aware Staggering
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys57074.2022.00151openalex-snapshot
Quantifying Throughput of Basic Blocks on ARM Microarchitectures by Static Code Analyzers: A Case Study on Kunpeng 920
inferred← citeshttps://doi.org/10.1109/ipdpsw55747.2022.00050openalex-snapshot
High-Performance GraphBLAS Backend Prototype for NEC SX-Aurora TSUBASA
inferred← citeshttps://doi.org/10.1109/ipdpsw63119.2024.00012openalex-snapshot
Towards Dynamic Autotuning of SpMV in CUSP Library
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00054openalex-snapshot
A Conflict-aware Divide-and-Conquer Algorithm for Symmetric Sparse Matrix-Vector Multiplication
inferred← citeshttps://doi.org/10.1145/3569951.3597583openalex-snapshot
A Further Study of Linux Kernel Hugepages on A64FX with FLASH, an Astrophysical Simulation Code
inferred← citeshttps://doi.org/10.1145/3595178openalex-snapshot
Cache Optimization and Performance Modeling of Batched, Small, and Rectangular Matrix Multiplication on Intel, AMD, and Fujitsu Processors
inferred← citeshttps://doi.org/10.1145/3624062.3624181openalex-snapshot
Porting Batched Iterative Solvers onto Intel GPUs with SYCL
inferred← citeshttps://doi.org/10.1145/3624062.3624198openalex-snapshot
Modelling Data Locality of Sparse Matrix-Vector Multiplication on the A64FX
inferred← citeshttps://doi.org/10.1145/3629520openalex-snapshot
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads
inferred← citeshttps://doi.org/10.1145/3703001.3724385openalex-snapshot
Performance Evaluation of Loop Body Splitting for Fast Modal Filtering in SCALE-DG on A64FX
inferred← citeshttps://doi.org/10.1145/3803015openalex-snapshot
Towards Efficient Symmetric Sparse Matrix-Vector Multiplication on Multi-Cores
inferred← citeshttps://doi.org/10.14778/3611479.3611485openalex-snapshot
Analyzing Vectorized Hash Tables across CPU Architectures
inferred← citeshttps://doi.org/10.22323/1.430.0285openalex-snapshot
MRHS multigrid solver for Wilson-clover fermions
inferred← citeshttps://doi.org/10.2298/csis230819005ropenalex-snapshot
SPC5: An efficient SpMV framework vectorized using ARM SVE and x86 AVX-512
inferred← citeshttps://doi.org/10.25209/2079-3316-2022-13-1-131-194openalex-snapshot
Modern server ARM processors for supercomputers: A64FX and others. Initial data of benchmarks
inferred← citeshttps://doi.org/10.25209/2079-3316-2022-13-1-63-129openalex-snapshot
Modern server ARM processors for supercomputers: A64FX and others. Initial data of benchmarks
inferred← citeshttps://doi.org/10.3389/fhpcp.2026.1664774openalex-snapshot
Toward energy-efficiency: CNTD_MERIC approach for energy-aware MPI applications
inferred← citeshttps://doi.org/10.7287/peerj-cs.769v0.1/reviews/1openalex-snapshot
Peer Review #1 of "A fast vectorized sorting implementation based on the ARM scalable vector extension (SVE) (v0.1)"
inferred← citeshttps://doi.org/10.7287/peerj-cs.769v0.1/reviews/2openalex-snapshot
Peer Review #2 of "A fast vectorized sorting implementation based on the ARM scalable vector extension (SVE) (v0.1)"
inferred← citeshttps://doi.org/10.7287/peerj-cs.769v0.2/reviews/1openalex-snapshot
Peer Review #1 of "A fast vectorized sorting implementation based on the ARM scalable vector extension (SVE) (v0.2)"
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