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Efficient communication using message prediction for clusters of multiprocessors

https://doi.org/10.1002/cpe.697
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1006/jpdc.1998.1512openalex-snapshot
Buffer-Safe and Cost-Driven Communication Optimization
inferredcites →https://doi.org/10.1007/10720115_12openalex-snapshot
Efficient Communication Using Message Prediction for Cluster of Multiprocessors
inferredcites →https://doi.org/10.1007/bfb0052218openalex-snapshot
Characterization of communication patterns in message-passing parallel scientific application programs
inferredcites →https://doi.org/10.1007/bfb0098001openalex-snapshot
Implementation and evaluation of MPI on an SMP cluster
inferredcites →https://doi.org/10.1016/0743-7315(91)90014-zopenalex-snapshot
Tolerating latency through software-controlled prefetching in shared-memory multiprocessors
inferredcites →https://doi.org/10.1023/a:1019018423211openalex-snapshot
Efficient layering for high speed communication: the MPI over Fast Messages (FM) experience
inferredcites →https://doi.org/10.1109/40.342015openalex-snapshot
Myrinet: a gigabit-per-second local area network
inferredcites →https://doi.org/10.1109/40.671404openalex-snapshot
The Virtual Interface Architecture
inferredcites →https://doi.org/10.1109/40.683106openalex-snapshot
Designing for a gigahertz [guTS integer processor]
inferredcites →https://doi.org/10.1109/71.395402openalex-snapshot
Sequential hardware prefetching in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/71.508249openalex-snapshot
A unified framework for optimizing communication in data-parallel programs
inferredcites →https://doi.org/10.1109/hpca.1997.569569openalex-snapshot
Proceedings Third International Symposium on High-Performance Computer Architecture
inferredcites →https://doi.org/10.1109/hpca.1997.569693openalex-snapshot
Towards a communication characterization methodology for parallel applications
inferredcites →https://doi.org/10.1109/hpca.1997.569699openalex-snapshot
Architectural support for reducing communication overhead in multiprocessor interconnection networks
inferredcites →https://doi.org/10.1109/hpca.1999.744359openalex-snapshot
Improving CC-NUMA performance using Instruction-based Prediction
inferredcites →https://doi.org/10.1109/ipps.1998.669932openalex-snapshot
Pin-down cache: a virtual memory management technique for zero-copy communication
inferredcites →https://doi.org/10.1109/ipps.1999.760434openalex-snapshot
Hiding communication latency in reconfigurable message-passing environments
inferredcites →https://doi.org/10.1109/ipps.1999.760457openalex-snapshot
Implementing efficient MPI on LAPI for IBM RS/6000 SP systems: Experiences and performance evaluation
inferredcites →https://doi.org/10.1109/isca.1992.753322openalex-snapshot
Active Messages: A Mechanism for Integrated Communication and Computation
inferredcites →https://doi.org/10.1109/isca.1995.524560openalex-snapshot
Speeding up irregular applications in shared-memory multiprocessors: memory binding and group prefetching
inferredcites →https://doi.org/10.1109/isca.2004.1310749openalex-snapshot
Proceedings 31st Annual International Symposium on Computer Architecture
inferredcites →https://doi.org/10.1109/shpcc.1994.296645openalex-snapshot
Parallel Spectral Transform Shallow Water Model: a runtime-tunable parallel benchmark code
inferredcites →https://doi.org/10.1145/139669.140382openalex-snapshot
Active messages
inferredcites →https://doi.org/10.1145/168619.168634openalex-snapshot
Fbufs: a high-bandwidth cross-domain transfer facility
inferredcites →https://doi.org/10.1145/223982.224423openalex-snapshot
Speeding up irregular applications in shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/224056.224061openalex-snapshot
U-Net
inferredcites →https://doi.org/10.1145/264107openalex-snapshot
Proceedings of the 24th annual international symposium on Computer architecture
inferredcites →https://doi.org/10.1145/279358.279386openalex-snapshot
Using prediction to accelerate coherence protocols
inferredcites →https://doi.org/10.1145/300979.300994openalex-snapshot
Memory sharing predictor: the key to a speculative coherent DSM
inferredcites →https://doi.org/10.1145/3341301openalex-snapshot
Proceedings of the 27th ACM Symposium on Operating Systems Principles

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.958openalex-snapshot
Applying fuzzy logic and genetic algorithms to enhance the efficacy of the PID controller in buffer overflow elimination for better channel response timeliness over the Internet
inferred← citeshttps://doi.org/10.1007/978-3-540-24685-5_2openalex-snapshot
Predicting MPI Buffer Addresses
inferred← citeshttps://doi.org/10.1109/ccece.2007.239openalex-snapshot
Using the Cell Processor As a Network Assist to Minimize Latency
inferred← citeshttps://doi.org/10.1109/hpcsa.2002.1019130openalex-snapshot
Architectural extensions to support effcient communication using message prediction
inferred← citeshttps://doi.org/10.1109/ipdps.2003.1213167openalex-snapshot
Exploring the predictability of MPI messages
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370470openalex-snapshot
Linking Compilation and Visualization for Massively Parallel Programs
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536190openalex-snapshot
Extended characterization of DMA transfers on the Cell BE processor
inferred← citeshttps://doi.org/10.1109/ipdps.2009.5161035openalex-snapshot
An approach for matching communication patterns in parallel applications
inferred← citeshttps://doi.org/10.1109/lcn.2004.20openalex-snapshot
An evaluation of the Myrinet/GM2 two-port networks
inferred← citeshttps://doi.org/10.1109/pacrim.2009.5291299openalex-snapshot
Characterization of single-port and multi-port collective communication operations on the Cell BE processor
inferred← citeshttps://doi.org/10.1145/1944862.1944891openalex-snapshot
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
inferred← citeshttps://doi.org/10.32388/lv7klkopenalex-snapshot
COVID-19 Crisis: Exploring Challenges, Opportunities, and Cautions
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