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Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

https://doi.org/10.1002/cta.3030
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/adma.201804682openalex-snapshot
Potential 2D Materials with Phase Transitions: Structure, Synthesis, and Device Applications
inferredcites →https://doi.org/10.1002/cta.2286openalex-snapshot
Template attacks exploiting static power and application to CMOS lightweight crypto‐hardware
inferredcites →https://doi.org/10.1002/cta.2296openalex-snapshot
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
inferredcites →https://doi.org/10.1002/cta.2398openalex-snapshot
Impact of the RT‐level architecture on the power performance of tunnel transistor circuits
inferredcites →https://doi.org/10.1002/cta.2731openalex-snapshot
Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage
inferredcites →https://doi.org/10.1002/cta.2792openalex-snapshot
A design of cellular automata‐based PUF and its implementation on FPGA
inferredcites →https://doi.org/10.1002/smll.202003319openalex-snapshot
Emerging Group‐VI Elemental 2D Materials: Preparations, Properties, and Device Applications
inferredcites →https://doi.org/10.1016/j.spmi.2018.12.010openalex-snapshot
Implementation of Physical Unclonable Functions using hetero junction based GAA TFET
inferredcites →https://doi.org/10.1016/j.sse.2014.12.002openalex-snapshot
Universal analytic model for tunnel FET circuit simulation
inferredcites →https://doi.org/10.1016/j.sse.2016.07.006openalex-snapshot
A review of emerging non-volatile memory (NVM) technologies and applications
inferredcites →https://doi.org/10.1049/iet-cds.2018.5297openalex-snapshot
Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks
inferredcites →https://doi.org/10.1049/iet-cds.2019.0504openalex-snapshot
Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator
inferredcites →https://doi.org/10.1109/access.2018.2881533openalex-snapshot
A Survey on Energy Efficient Narrowband Internet of Things (NBIoT): Architecture, Application and Challenges
inferredcites →https://doi.org/10.1109/icemelec.2016.8074564openalex-snapshot
Exploiting the steep subthreshold slope characteristics of tunnel transistors for wide tuning range voltage controlled ring oscillator (VCRO) design at scaled supply voltages down to 150mV
inferredcites →https://doi.org/10.1109/icrc.2017.8123640openalex-snapshot
Low-Power and Secure Lightweight Cryptography Via TFET-Based Energy Recovery Circuits
inferredcites →https://doi.org/10.1109/iedm.2016.7838450openalex-snapshot
Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at Vds = 0.3 V
inferredcites →https://doi.org/10.1109/inis.2017.28openalex-snapshot
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms
inferredcites →https://doi.org/10.1109/isscc.2014.6757434openalex-snapshot
16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS
inferredcites →https://doi.org/10.1109/isscc.2015.7063022openalex-snapshot
14.2 A physically unclonable function with BER <10−8 for robust chip authentication using oscillator collapse in 40nm CMOS
inferredcites →https://doi.org/10.1109/isvlsi.2016.93openalex-snapshot
Hardware Security Challenges Beyond CMOS: Attacks and Remedies
inferredcites →https://doi.org/10.1109/jeds.2016.2545978openalex-snapshot
A Review of Sharp-Switching Devices for Ultra-Low Power Applications
inferredcites →https://doi.org/10.1109/jeds.2018.2825639openalex-snapshot
Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations
inferredcites →https://doi.org/10.1109/jetcas.2014.2361068openalex-snapshot
Tunnel FET RF Rectifier Design for Energy Harvesting Applications
inferredcites →https://doi.org/10.1109/jiot.2019.2935189openalex-snapshot
IoT: Internet of Threats? A Survey of Practical Security Vulnerabilities in Real IoT Devices
inferredcites →https://doi.org/10.1109/jproc.2013.2252317openalex-snapshot
Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking
inferredcites →https://doi.org/10.1109/jproc.2014.2387353openalex-snapshot
Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications
inferredcites →https://doi.org/10.1109/jssc.2016.2519383openalex-snapshot
An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations
inferredcites →https://doi.org/10.1109/jssc.2016.2558490openalex-snapshot
$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS
inferredcites →https://doi.org/10.1109/jssc.2018.2886350openalex-snapshot
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS
inferredcites →https://doi.org/10.1109/jxcdc.2015.2418033openalex-snapshot
Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits
inferredcites →https://doi.org/10.1109/mcas.2017.2713305openalex-snapshot
A Retrospective and a Look Forward: Fifteen Years of Physical Unclonable Function Advancement
inferredcites →https://doi.org/10.1109/mce.2018.2851721openalex-snapshot
Nanoelectronic Security Designs for Resource-Constrained Internet of Things Devices: Finding Security Solutions with Nanoelectronic Hardwares
inferredcites →https://doi.org/10.1109/tcad.2018.2889770openalex-snapshot
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies
inferredcites →https://doi.org/10.1109/tcsi.2020.3010803openalex-snapshot
Challenges and Solutions of the TFET Circuit Design
inferredcites →https://doi.org/10.1109/tcsii.2016.2530800openalex-snapshot
A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards
inferredcites →https://doi.org/10.1109/tcsii.2021.3057678openalex-snapshot
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption
inferredcites →https://doi.org/10.1109/ted.2016.2539209openalex-snapshot
Study of Random Variation in Germanium-Source Vertical Tunnel FET
inferredcites →https://doi.org/10.1109/ted.2018.2808040openalex-snapshot
Sensitivity Challenge of Steep Transistors
inferredcites →https://doi.org/10.1109/ted.2018.2846782openalex-snapshot
Study on Random Dopant Fluctuation in Core–Shell Tunneling Field-Effect Transistors
inferredcites →https://doi.org/10.1109/tetc.2016.2559159openalex-snapshot
Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs
inferredcites →https://doi.org/10.1109/tmscs.2016.2519902openalex-snapshot
A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
inferredcites →https://doi.org/10.1109/tvlsi.2019.2914609openalex-snapshot
Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems
inferredcites →https://doi.org/10.1145/3372780.3378175openalex-snapshot
Hardware Security For and Beyond CMOS Technology
inferredcites →https://doi.org/10.3850/9783981537079_0993openalex-snapshot
Using Emerging Technologies for Hardware Security Beyond PUFs
inferredcites →https://doi.org/10.6028/nist.sp.800-22openalex-snapshot
A statistical test suite for random and pseudorandom number generators for cryptographic applications

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-21514-8_27openalex-snapshot
A Reconfigurable Arbiter PUF Based on VGSOT MTJ
inferred← citeshttps://doi.org/10.1007/978-3-031-48121-5_39openalex-snapshot
On Enhancing the Throughput of the Latched Ring Oscillator TRNG on FPGA
inferred← citeshttps://doi.org/10.1016/j.mejo.2021.105320openalex-snapshot
Negative capacitance FETs for energy efficient and hardware secure logic designs
inferred← citeshttps://doi.org/10.1016/j.mejo.2022.105445openalex-snapshot
A reconfigurable PUF structure with dual working modes based on entropy separation model
inferred← citeshttps://doi.org/10.1016/j.micpro.2025.105170openalex-snapshot
A reconfigurable PUF and TRNG design based on multiplexers for securing IoT applications
inferred← citeshttps://doi.org/10.1038/s41598-024-71730-7openalex-snapshot
A robust deep learning attack immune MRAM-based physical unclonable function
inferred← citeshttps://doi.org/10.1109/icedge67252.2025.11412853openalex-snapshot
Detection of DNS Over HTTPS Tunneling Attacks in Smart Home IoT Devices Through Optimized Feature Analysis
inferred← citeshttps://doi.org/10.1109/tmag.2025.3574994openalex-snapshot
Unified PUF and TRNG Design Using SOT-MTJ Crossbar Array
inferred← citeshttps://doi.org/10.1145/3690407.3690488openalex-snapshot
Tunnel construction process monitoring system based on Internet of Things technology
inferred← citeshttps://doi.org/10.1155/2022/4123437openalex-snapshot
Analysis of Cardiovascular Disease Angiography Process Based on Rough Set and Internet of Things
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