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A binary‐based on‐chip CNN solution for pixel‐level snakes
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/(sici)1097-007x(199901/02)27:1<87::aid-cta42>3.0.co;2-vopenalex-snapshot
CNN template robustness with different output nonlinearities
inferredcites →https://doi.org/10.1002/cta.302openalex-snapshot
Pixel‐level snakes on the CNNUM: algorithm design, on‐chip implementation and applications
inferredcites →https://doi.org/10.1007/bf01239169openalex-snapshot
High resolution CMOS current comparators: design and applications to current-mode function generation
inferredcites →https://doi.org/10.1007/bf01385685openalex-snapshot
A geometric model for active contours in image processing
inferredcites →https://doi.org/10.1016/0895-6111(94)00040-9openalex-snapshot
A dynamic finite element surface model for segmentation and tracking in multidimensional medical images with application to cardiac 4D image analysis
inferredcites →https://doi.org/10.1016/s0262-8856(02)00153-1openalex-snapshot
Cellular neural networks and active contours: a tool for image segmentation
inferredcites →https://doi.org/10.1016/s1361-8415(96)80007-7openalex-snapshot
Deformable models in medical image analysis: a survey
inferredcites →https://doi.org/10.1017/cbo9780511754494openalex-snapshot
Cellular Neural Networks and Visual Computing
inferredcites →https://doi.org/10.1023/a:1008153320440openalex-snapshot
Computing with Front Propagation: Active Contour And Skeleton Models In Continuous-Time CNN
inferredcites →https://doi.org/10.1109/34.368173openalex-snapshot
Shape modeling with front propagation: a level set approach
inferredcites →https://doi.org/10.1109/81.915384openalex-snapshot
A new cell output nonlinearity for dense cellular nonlinear network integration
inferredcites →https://doi.org/10.1109/cnna.2005.1543214openalex-snapshot
On the Emulation of Large-Neighborhood Templates with Binary CNN-Based Architectures
inferredcites →https://doi.org/10.1109/ijcnn.2002.1007818openalex-snapshot
An analog array processor hardware realization with multiple new features
inferredcites →https://doi.org/10.1109/iscas.2005.1465488openalex-snapshot
A One-Quadrant Discrete-Time Cellular Neural Network Architecture for Pixel-Level Snakes: B/W Processing
inferredcites →https://doi.org/10.1109/iscas.2005.1465492openalex-snapshot
Template Design for Binary-Programmable Cellular Nonlinear Networks
inferredcites →https://doi.org/10.1109/jssc.2002.808305openalex-snapshot
Understanding MOSFET mismatch for analog design
inferredcites →https://doi.org/10.1109/tcsi.2004.827621openalex-snapshot
ACE16k: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
inferredcites →https://doi.org/10.1109/tcsi.2004.827625openalex-snapshot
Design of the Processing Core of a Mixed-Signal CMOS DTCNN Chip for Pixel-Level Snakes
inferredcites →https://doi.org/10.1109/tcsi.2004.827637openalex-snapshot
Implementation of a Pixel-Level Snake Algorithm on a CNNUM-Based Chip Set Architecture
inferredcites →https://doi.org/10.1109/tcsi.2004.840093openalex-snapshot
A general-purpose processor-per-pixel analog SIMD vision chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cta.1823openalex-snapshot
Implementation of cellular genetic algorithms on a CNN chip: Simulations and experimental results
inferred← citeshttps://doi.org/10.1002/cta.1850openalex-snapshot
Split and shift methodology on cellular processor arrays: area saving versus time penalty
inferred← citeshttps://doi.org/10.1002/cta.2935openalex-snapshot
An improved approach for mining association rules in parallel using Spark Streaming
inferred← citeshttps://doi.org/10.1002/cta.481openalex-snapshot
Single‐layer perceptron and dynamic neuron implementing linearly non‐separable Boolean functions
inferred← citeshttps://doi.org/10.1002/cta.614openalex-snapshot
Asynchronous demodulation technique for use in vision sensor image classification and segmentation
inferred← citeshttps://doi.org/10.1109/cnna.2008.4588651openalex-snapshot
Template-oriented hardware design based on shape analysis of 2D CNN operators in CNN template libraries and applications
inferred← citeshttps://doi.org/10.1109/ecctd.2007.4529543openalex-snapshot
Verification of Split&Shift techniques for CNN hardware reduction
inferred← citeshttps://doi.org/10.1109/ecctd.2007.4529544openalex-snapshot
Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models
inferred← citeshttps://doi.org/10.1109/icm.2009.5418678openalex-snapshot
Handsheet for full-custom circuit design
inferred← citeshttps://doi.org/10.1109/iscas.2007.377966openalex-snapshot
Area and Time Efficient Cellular Non-linear Networks
inferred← citeshttps://doi.org/10.5772/7068openalex-snapshot
An FPGA-based Topographic Computer for Binary Image Processing
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