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UMTS security: system architecture and hardware implementation

https://doi.org/10.1002/wcm.367
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-44499-8_9openalex-snapshot
A Comparative Study of Performance of AES Final Candidates Using FPGAs
inferredcites →https://doi.org/10.1007/3-540-44709-1_6openalex-snapshot
Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
inferredcites →https://doi.org/10.1007/3-540-44709-1_8openalex-snapshot
Two Methods of Rijndael Implementation in Reconfigurable Hardware
inferredcites →https://doi.org/10.1007/3-540-45439-x_17openalex-snapshot
On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms
inferredcites →https://doi.org/10.1007/3-540-45811-5_4openalex-snapshot
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI
inferredcites →https://doi.org/10.1007/bfb0052334openalex-snapshot
New block encryption algorithm MISTY
inferredcites →https://doi.org/10.1109/12.238496openalex-snapshot
On computing multiplicative inverses in GF(2/sup m/)
inferredcites →https://doi.org/10.1109/92.894168openalex-snapshot
Analysis of power dissipation in double edge-triggered flip-flops
inferredcites →https://doi.org/10.1109/92.931230openalex-snapshot
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
inferredcites →https://doi.org/10.1109/jssc.2002.808300openalex-snapshot
Design and performance testing of a 2.29-GB/s rijndael processor
inferredcites →https://doi.org/10.1109/tc.1985.1676616openalex-snapshot
VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
inferredcites →https://doi.org/10.1109/tc.2002.1146712openalex-snapshot
Architectures and VLSI implementations of the AES-Proposal Rijndael
inferredcites →https://doi.org/10.5860/choice.34-4512openalex-snapshot
Handbook of applied cryptography
inferredcites →https://doi.org/10.6028/nist.sp.800-38aopenalex-snapshot
Recommendation for block cipher modes of operation :

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-642-00730-9_18openalex-snapshot
Extended Models for Message Authentication
inferred← citeshttps://doi.org/10.1007/s11859-012-0833-4openalex-snapshot
A solution to the anonymity of the mobile subscriber
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2007.05.003openalex-snapshot
Platform independent overall security architecture in multi-processor system-on-chip integrated circuits for use in mobile phones and handheld devices
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103212openalex-snapshot
FPGA implementation of an optimized A5/3 encryption algorithm
inferred← citeshttps://doi.org/10.1109/cybersec.2014.6913969openalex-snapshot
Modifying authentication techniques in mobile communication systems
inferred← citeshttps://doi.org/10.1109/eurcon.2009.5167894openalex-snapshot
Architecture & system design of Authentication, Authorization, & Accounting services
inferred← citeshttps://doi.org/10.1109/ibcast.2017.7868088openalex-snapshot
Performance comparison of KASUMI and hardware architecture optimization of f8 and f9 algorithms for 3g UMTS networks
inferred← citeshttps://doi.org/10.1109/icise.2009.478openalex-snapshot
Design of a High Security GSM/UMTS Inter-System
inferred← citeshttps://doi.org/10.1109/ncg.2018.8593101openalex-snapshot
Area-Efficient Architectures of KASUMI Block Cipher
inferred← citeshttps://doi.org/10.1109/tdsc.2016.2620437openalex-snapshot
Architecture Design of an Area Efficient High Speed Crypto Processor for 4G LTE
inferred← citeshttps://doi.org/10.17781/p001336openalex-snapshot
Enhanced Mobile Authentication Techniques
inferred← citeshttps://doi.org/10.3390/jcp6040122openalex-snapshot
TALOS: An Ultra-Efficient Area-Space 6G CryptoProcessor Leveraging Reusable Hardware Security Modules
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