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Power-Saving Scheduling for Weakly Dynamic Voltage Scaling Devices
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-0-585-29603-6_17openalex-snapshot
Scheduling for Reduced CPU Energy
inferredcites →https://doi.org/10.1016/b978-155860702-6/50016-8openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.1016/s0167-6377(01)00102-xopenalex-snapshot
Hardness of approximation of the discrete time-cost tradeoff problem
inferredcites →https://doi.org/10.1016/s0167-6377(97)00010-2openalex-snapshot
Single machine scheduling with discretely controllable processing times
inferredcites →https://doi.org/10.1109/92.645069openalex-snapshot
Embedded power supply for low-power DSP
inferredcites →https://doi.org/10.1109/92.748197openalex-snapshot
Segmented bus design for low-power systems
inferredcites →https://doi.org/10.1109/date.2002.998258openalex-snapshot
Competitive analysis of dynamic power management strategies for systems with multiple power saving states
inferredcites →https://doi.org/10.1109/icce.2001.935282openalex-snapshot
A dynamic-voltage-adjustment mechanism in reducing the power consumption of flash memory for portable devices
inferredcites →https://doi.org/10.1109/sfcs.1994openalex-snapshot
Proceedings 35th Annual Symposium on Foundations of Computer Science
inferredcites →https://doi.org/10.1109/sfcs.1995.492493openalex-snapshot
A scheduling model for reduced CPU energy
inferredcites →https://doi.org/10.1109/tcad.2003.814245openalex-snapshot
Energy-conscious, deterministic i/o device scheduling in hard real-time systems
inferredcites →https://doi.org/10.1109/tvlsi.2003.810801openalex-snapshot
Variable voltage task scheduling algorithms for minimizing energy/power
inferredcites →https://doi.org/10.1145/2627369openalex-snapshot
Proceedings of the 2014 international symposium on Low power electronics and design
inferredcites →https://doi.org/10.1145/277044.277088openalex-snapshot
Power optimization of variable voltage core-based systems
inferredcites →https://doi.org/10.1145/280756.280790openalex-snapshot
The simulation and evaluation of dynamic voltage scaling algorithms
inferredcites →https://doi.org/10.1145/280756.280894openalex-snapshot
Voltage scheduling problem for dynamically variable voltage processors
inferredcites →https://doi.org/10.1145/309847.309901openalex-snapshot
Power conscious fixed priority scheduling for hard real-time systems
inferredcites →https://doi.org/10.1145/321738.321743openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.1145/321906.321909openalex-snapshot
Fast Approximation Algorithms for the Knapsack and Sum of Subset Problems
inferredcites →https://doi.org/10.1145/337292.337785openalex-snapshot
Run-time voltage hopping for low-power real-time systems
inferredcites →https://doi.org/10.1145/344166.344530openalex-snapshot
Voltage scheduling in the IpARM microprocessor system
inferredcites →https://doi.org/10.1145/378239.378551openalex-snapshot
Low-energy intra-task voltage scheduling using static timing analysis
inferredcites →https://doi.org/10.1145/378239.379074openalex-snapshot
Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors
inferredcites →https://doi.org/10.1145/383082.383089openalex-snapshot
Energy priority scheduling for variable voltage processors
inferredcites →https://doi.org/10.1145/383082.383162openalex-snapshot
A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applications
inferredcites →https://doi.org/10.1145/383082.383168openalex-snapshot
Variable voltage task scheduling algorithms for minimizing energy
inferredcites →https://doi.org/10.1145/606603.606606openalex-snapshot
Design theory and implementation for low-power segmented bus systems
inferredcites →https://doi.org/10.1145/775832.776059openalex-snapshot
A survey of techniques for energy efficient on-chip communication
inferredcites →https://doi.org/10.1145/967900.968072openalex-snapshot
Profit-driven uniprocessor scheduling with energy and timing constraints
inferredcites →https://doi.org/10.1287/moor.23.4.909openalex-snapshot
Approximation Algorithms for the Discrete Time-Cost Tradeoff Problem
inferredcites →https://doi.org/10.1287/opre.45.2.302openalex-snapshot
Complexity of the Discrete Time-Cost Tradeoff Problem for Project Networks
inferredcites →https://doi.org/10.5555/602902.602984openalex-snapshot
Power optimization of real-time embedded systems on variable speed processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cplx.21561openalex-snapshot
Complexity of a problem of energy efficient real‐time task scheduling on a multicore processor
inferred← citeshttps://doi.org/10.1007/11671411_24openalex-snapshot
Speed Scaling of Tasks with Precedence Constraints
inferred← citeshttps://doi.org/10.1007/978-3-540-27810-8_3openalex-snapshot
Getting the Best Response for Your Erg
inferred← citeshttps://doi.org/10.1007/978-3-540-77090-9_56openalex-snapshot
Energy-Efficiency on a Variable-Bitrate Device
inferred← citeshttps://doi.org/10.1007/978-3-642-31155-0_22openalex-snapshot
Non-preemptive Speed Scaling
inferred← citeshttps://doi.org/10.1007/978-3-662-44465-8_31openalex-snapshot
New Results for Non-Preemptive Speed Scaling
inferred← citeshttps://doi.org/10.1007/s00224-007-9070-1openalex-snapshot
Speed Scaling of Tasks with Precedence Constraints
inferred← citeshttps://doi.org/10.1007/s00453-012-9678-7openalex-snapshot
Speed Scaling on Parallel Processors
inferred← citeshttps://doi.org/10.1007/s10951-009-0123-yopenalex-snapshot
Power-aware scheduling for makespan and flow
inferred← citeshttps://doi.org/10.1007/s10951-013-0312-6openalex-snapshot
Non-preemptive speed scaling
inferred← citeshttps://doi.org/10.1007/s11265-008-0280-9openalex-snapshot
Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device
inferred← citeshttps://doi.org/10.1016/j.apm.2013.10.023openalex-snapshot
A Monte Carlo algorithm for real time task scheduling on multi-core processors with software controlled dynamic voltage scaling
inferred← citeshttps://doi.org/10.1016/j.apm.2013.12.009openalex-snapshot
Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling
inferred← citeshttps://doi.org/10.1016/j.ejor.2018.02.059openalex-snapshot
Resource cost aware scheduling
inferred← citeshttps://doi.org/10.1016/j.kijoms.2015.11.008openalex-snapshot
Release Round Robin: R3 an energy-aware non-clairvoyant scheduling on speed bounded processors
inferred← citeshttps://doi.org/10.1109/aspdac.2007.358009openalex-snapshot
Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems
inferred← citeshttps://doi.org/10.1109/aspdac.2007.358098openalex-snapshot
Flow Time Minimization under Energy Constraints
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys53884.2021.00317openalex-snapshot
A Power Consumption Perception and Dynamic Adjustment Model for Embedded Real-Time Systems
inferred← citeshttps://doi.org/10.1109/ispa.2008.127openalex-snapshot
Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds
inferred← citeshttps://doi.org/10.1109/ispa.2008.128openalex-snapshot
Energy Optimal Scheduling on Multiprocessors with Migration
inferred← citeshttps://doi.org/10.1109/rtcsa.2007.37openalex-snapshot
Energy-Efficient Scheduling for Real-Time Systems on Dynamic Voltage Scaling (DVS) Platforms
inferred← citeshttps://doi.org/10.1109/rtss.2005.44openalex-snapshot
Voltage Scaling Scheduling for Periodic Real-Time Tasks in Reward Maximization
inferred← citeshttps://doi.org/10.1109/sutc.2008.54openalex-snapshot
Energy-Efficient Real-Time Co-scheduling of Multimedia DSP Jobs
inferred← citeshttps://doi.org/10.1109/tc.2011.40openalex-snapshot
Modeling Energy-Time Trade-Offs in VLSI Computation
inferred← citeshttps://doi.org/10.1145/1134650.1134673openalex-snapshot
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor
inferred← citeshttps://doi.org/10.1145/1148109.1148140openalex-snapshot
Power-aware scheduling for makespan and flow
inferred← citeshttps://doi.org/10.1145/1159974.1134673openalex-snapshot
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor
inferred← citeshttps://doi.org/10.1145/1248377.1248424openalex-snapshot
Speed scaling on parallel processors
inferred← citeshttps://doi.org/10.1145/1367064.1367078openalex-snapshot
Getting the best response for your erg
inferred← citeshttps://doi.org/10.48550/arxiv.cs/0605126openalex-snapshot
Power-aware scheduling for makespan and flow
inferred← citeshttps://doi.org/10.5121/ijcsit.2011.3215openalex-snapshot
Energy Efficient Task Scheduling of Send-Receive Task Graphs on Distributed Multi-Core Processors with Software Controlled Dynamic Voltage Scaling
inferred← citeshttps://doi.org/10.7916/d8z60wdxopenalex-snapshot
Resource Cost Aware Scheduling Problems
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