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Improved Higher-Order Side-Channel Attacks with FPGA Experiments
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11502760_28openalex-snapshot
A Side-Channel Analysis Resistant Description of the AES S-Box
inferredcites →https://doi.org/10.1007/3-540-44499-8openalex-snapshot
Cryptographic Hardware and Embedded Systems — CHES 2000
inferredcites →https://doi.org/10.1007/3-540-44499-8_19openalex-snapshot
Using Second-Order Power Analysis to Attack DPA Resistant Software
inferredcites →https://doi.org/10.1007/3-540-44499-8_5openalex-snapshot
Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies
inferredcites →https://doi.org/10.1007/3-540-44709-1openalex-snapshot
Cryptographic Hardware and Embedded Systems — CHES 2001
inferredcites →https://doi.org/10.1007/3-540-44709-1_26openalex-snapshot
An Implementation of DES and AES, Secure against Some Attacks
inferredcites →https://doi.org/10.1007/3-540-48059-5_15openalex-snapshot
DES and Differential Power Analysis The “Duplication” Method
inferredcites →https://doi.org/10.1007/3-540-48405-1openalex-snapshot
Advances in Cryptology — CRYPTO’ 99
inferredcites →https://doi.org/10.1007/3-540-48405-1_26openalex-snapshot
Towards Sound Approaches to Counteract Power-Analysis Attacks
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_1openalex-snapshot
Towards Efficient Second-Order Power Analysis
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_2openalex-snapshot
Correlation Power Analysis with a Leakage Model
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_3openalex-snapshot
Power analysis of an FPGA - Implementation of Rijndael: Is pipelining a DPA countermeasure?
inferredcites →https://doi.org/10.1007/978-3-540-30574-3_24openalex-snapshot
Side-Channel Leakage of Masked CMOS Gates
inferredcites →https://doi.org/10.1007/978-3-540-45238-6openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2003
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_3openalex-snapshot
Hidden Markov Model Cryptanalysis
inferredcites →https://doi.org/10.1007/b99451openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004, Proceedings
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/cdc.2002.1184857openalex-snapshot
Variance estimation and ranking of Gaussian mixture distributions in target tracking applications
inferredcites →https://doi.org/10.1109/itcc.2004.1286711openalex-snapshot
Power-analysis attack on an ASIC AES implementation
inferredcites →https://doi.org/10.1109/itcc.2005.213openalex-snapshot
On the masking countermeasure and higher-order power analysis attacks
inferredcites →https://doi.org/10.1109/tc.2002.1004593openalex-snapshot
Examining smart-card security under the threat of power analysis attacks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers
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Towards Security Limits in Side-Channel Attacks
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Template Attacks on Masking—Resistance Is Futile
inferred← citeshttps://doi.org/10.1007/978-0-387-71817-0_11openalex-snapshot
Secure and Efficient Implementation of Symmetric Encryption Schemes using FPGAs
inferred← citeshttps://doi.org/10.1007/978-1-4614-6783-0_8openalex-snapshot
Toward the Evaluation of an Implementation Against Side-Channel Attacks
inferred← citeshttps://doi.org/10.1007/978-3-031-64399-6_4openalex-snapshot
Attacks on Protected Devices
inferred← citeshttps://doi.org/10.1007/978-3-319-01854-6_41openalex-snapshot
A Toolbox for DPA Attacks to Smart Cards
inferred← citeshttps://doi.org/10.1007/978-3-319-16295-9_7openalex-snapshot
On Efficient Leakage-Resilient Pseudorandom Functions with Hard-to-Invert Leakages
inferred← citeshttps://doi.org/10.1007/978-3-319-16763-3_3openalex-snapshot
Study of a Novel Software Constant Weight Implementation
inferred← citeshttps://doi.org/10.1007/978-3-319-31271-2_16openalex-snapshot
Higher-Order Threshold Implementation of the AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-319-75208-2_5openalex-snapshot
A Novel Use of Kernel Discriminant Analysis as a Higher-Order Side-Channel Distinguisher
inferred← citeshttps://doi.org/10.1007/978-3-319-79063-3_12openalex-snapshot
Faster Isogeny-Based Compressed Key Agreement
inferred← citeshttps://doi.org/10.1007/978-3-540-71039-4_8openalex-snapshot
Block Ciphers Implementations Provably Secure Against Second Order Side Channel Analysis
inferred← citeshttps://doi.org/10.1007/978-3-540-74462-7_10openalex-snapshot
Changing the Odds Against Masked Logic
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_2openalex-snapshot
Gaussian Mixture Models for Higher-Order Side Channel Analysis
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_3openalex-snapshot
Side Channel Cryptanalysis of a Higher Order Masking Scheme
inferred← citeshttps://doi.org/10.1007/978-3-540-74835-9_30openalex-snapshot
Analyzing Side Channel Leakage of Masked Implementations with Stochastic Methods
inferred← citeshttps://doi.org/10.1007/978-3-540-76788-6_21openalex-snapshot
Power Analysis Attacks on MDPL and DRSL Implementations
inferred← citeshttps://doi.org/10.1007/978-3-642-16767-6_3openalex-snapshot
Side-Channel Analysis – Mathematics Has Met Engineering
inferred← citeshttps://doi.org/10.1007/978-3-642-17401-8_19openalex-snapshot
Attack on a Higher-Order Masking of the AES Based on Homographic Functions
inferred← citeshttps://doi.org/10.1007/978-3-642-21040-2_14openalex-snapshot
Leakage Squeezing Countermeasure against High-Order Attacks
inferred← citeshttps://doi.org/10.1007/978-3-642-23951-9_16openalex-snapshot
Thwarting Higher-Order Side Channel Analysis with Additive and Multiplicative Maskings
inferred← citeshttps://doi.org/10.1007/978-3-642-27954-6_10openalex-snapshot
A First-Order Leak-Free Masking Countermeasure
inferred← citeshttps://doi.org/10.1007/978-3-642-31410-0_22openalex-snapshot
Optimal First-Order Masking with Linear and Non-linear Bijections
inferred← citeshttps://doi.org/10.1007/978-3-642-37288-9_6openalex-snapshot
On the Use of Shamir’s Secret Sharing against Side-Channel Analysis
inferred← citeshttps://doi.org/10.1007/978-3-642-42001-6_11openalex-snapshot
When Should an Implementation Attack Be Viewed as Successful?
inferred← citeshttps://doi.org/10.1007/978-3-662-46800-5_18openalex-snapshot
Verified Proofs of Higher-Order Masking
inferred← citeshttps://doi.org/10.1007/978-3-662-52993-5_12openalex-snapshot
There Is Wisdom in Harnessing the Strengths of Your Enemy: Customized Encoding to Thwart Side-Channel Attacks
inferred← citeshttps://doi.org/10.1007/978-3-662-53887-6_21openalex-snapshot
Taylor Expansion of Maximum Likelihood Attacks for Masked and Shuffled Implementations
inferred← citeshttps://doi.org/10.1007/978-94-007-1338-3_4openalex-snapshot
Countermeasures Against Physical Attacks in FPGAs
inferred← citeshttps://doi.org/10.1007/s10836-024-06149-zopenalex-snapshot
A Novel Two-Stage Model Based SCA against secAES
inferred← citeshttps://doi.org/10.1007/s11042-019-08592-zopenalex-snapshot
FPGA based generic RO TRNG architecture for image confusion
inferred← citeshttps://doi.org/10.1007/s11432-012-4588-5openalex-snapshot
Polar differential power attacks and evaluation
inferred← citeshttps://doi.org/10.1007/s12095-014-0113-6openalex-snapshot
Masking and leakage-resilient primitives: One, the other(s) or both?
inferred← citeshttps://doi.org/10.1007/s41635-021-00117-1openalex-snapshot
Methods and Analysis of Automated Trace Alignment Under Power Obfuscation in Side Channel Attacks
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2008.06.004openalex-snapshot
Dual-rail transition logic: A logic style for counteracting power analysis attacks
inferred← citeshttps://doi.org/10.1016/j.ins.2018.07.042openalex-snapshot
Multiple leakage samples based higher order optimal distinguisher
inferred← citeshttps://doi.org/10.1016/j.vlsi.2009.01.001openalex-snapshot
Vulnerability modeling of cryptographic hardware to power analysis attacks
inferred← citeshttps://doi.org/10.1049/iet-ifs:20070066openalex-snapshot
Security analysis of higher-order Boolean masking schemes for block ciphers (with conditions of perfect masking)
inferred← citeshttps://doi.org/10.1093/jigpal/jzv041openalex-snapshot
Design and optimization of the input modules of a DPA toolbox
inferred← citeshttps://doi.org/10.1109/access.2022.3185995openalex-snapshot
Fully-Digital Randomization Based Side-Channel Security—Toward Ultra-Low Cost-per-Security
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Power Variance Analysis breaks a masked ASIC implementation of AES
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RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs
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FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
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Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey
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Lightweight DPA resistant solution on FPGA to counteract power models
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Place-and-route impact on the security of DPL designs in FPGAs
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Formal security evaluation of hardware Boolean masking against second-order attacks
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Register leakage masking using Gray code
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Evaluation of countermeasure implementations based on Boolean masking to thwart side-channel attacks
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A new efficient interesting points enhanced electromagnetic attack on AT89S52
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An Overview of Power Analysis Attacks Against Field Programmable Gate Arrays
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DPL on Stratix II FPGA: What to Expect?
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Cross-Correlation Cartography
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A Taxonomy of Side-Channels
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Anatomy of Differential Power Analysis for AES
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Statistical Analysis of Second Order Differential Power Analysis
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Efficient Profiled Side-Channel Analysis of Masked Implementations, Extended
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Electromagnetic Radiations of FPGAs
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Seasoning effect based side channel attacks to AES implementation with phase change memory
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DPA on hardware implementations of Ascon and Keyak
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Trust Issues in COTS: The Challenges and Emerging Solution
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A Review and Comparison of AI-enhanced Side Channel Analysis
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On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography
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Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
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Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography
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Side-Channel Analysis Attacks on Hardware Implementations of Cryptographic Algorithms
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Advanced stochastic methods in side channel analysis on block ciphers in the presence of masking
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Differential Side Channel Analysis Attacks on FPGA Implementations of ARIA
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A Tale of Snakes and Horses: Amplifying Correlation Power Analysis on Quadratic Maps
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A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
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Security of cryptosystems against power-analysis attacks
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