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The “Backend Duplication” Method
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/1-4020-8147-2_10openalex-snapshot
Place and Route for Secure Standard Cell Design
inferredcites →https://doi.org/10.1007/3-540-44709-1openalex-snapshot
Cryptographic Hardware and Embedded Systems — CHES 2001
inferredcites →https://doi.org/10.1007/3-540-44709-1_21openalex-snapshot
Electromagnetic Analysis: Concrete Results
inferredcites →https://doi.org/10.1007/3-540-48059-5_15openalex-snapshot
DES and Differential Power Analysis The “Duplication” Method
inferredcites →https://doi.org/10.1007/3-540-48405-1openalex-snapshot
Advances in Cryptology — CRYPTO’ 99
inferredcites →https://doi.org/10.1007/3-540-68697-5openalex-snapshot
Advances in Cryptology — CRYPTO ’96
inferredcites →https://doi.org/10.1007/3-540-68697-5_9openalex-snapshot
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_21openalex-snapshot
Improving the Security of Dual-Rail Circuits
inferredcites →https://doi.org/10.1007/978-3-540-45238-6openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2003
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_11openalex-snapshot
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
inferredcites →https://doi.org/10.1007/b99451openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004, Proceedings
inferredcites →https://doi.org/10.1109/async.2002.1000311openalex-snapshot
Improving smart card security using self-timed circuits
inferredcites →https://doi.org/10.1109/date.2004.1268856openalex-snapshot
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
inferredcites →https://doi.org/10.1109/date.2004.1269113openalex-snapshot
CMOS structures suitable for secured hardware
inferredcites →https://doi.org/10.1109/date.2005.124openalex-snapshot
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
inferredcites →https://doi.org/10.5555/968879.969186openalex-snapshot
CMOS structures suitable for secured hardware
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11894063_21openalex-snapshot
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
inferred← citeshttps://doi.org/10.1007/978-3-319-66787-4_20openalex-snapshot
Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_29openalex-snapshot
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_6openalex-snapshot
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-78610-8_11openalex-snapshot
Physical Design of FPGA Interconnect to Prevent Information Leakage
inferred← citeshttps://doi.org/10.1007/978-3-540-85053-3_25openalex-snapshot
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
inferred← citeshttps://doi.org/10.1007/978-3-540-85893-5_15openalex-snapshot
A Practical DPA Countermeasure with BDD Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-14423-3_11openalex-snapshot
Power Analysis of Single-Rail Storage Elements as Used in MDPL
inferred← citeshttps://doi.org/10.1007/978-3-642-24209-0_1openalex-snapshot
Analysis of Nonparametric Estimation Methods for Mutual Information Analysis
inferred← citeshttps://doi.org/10.1007/978-3-662-44709-3_33openalex-snapshot
Early Propagation and Imbalanced Routing, How to Diminish in FPGAs
inferred← citeshttps://doi.org/10.1007/978-94-007-1338-3_4openalex-snapshot
Countermeasures Against Physical Attacks in FPGAs
inferred← citeshttps://doi.org/10.1007/s10617-008-9017-zopenalex-snapshot
Path switching: a technique to tolerate dual rail routing imbalances
inferred← citeshttps://doi.org/10.1007/s13389-015-0096-zopenalex-snapshot
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks
inferred← citeshttps://doi.org/10.1007/s13389-015-0105-2openalex-snapshot
Formally proved security of assembly code against power analysis
inferred← citeshttps://doi.org/10.1007/s13389-018-0185-xopenalex-snapshot
Your rails cannot hide from localized EM: how dual-rail logic fails on FPGAs—extended version
inferred← citeshttps://doi.org/10.1093/ietfec/e91-a.1.184openalex-snapshot
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
inferred← citeshttps://doi.org/10.1109/date.2010.5456932openalex-snapshot
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation
inferred← citeshttps://doi.org/10.1109/fdtc.2008.18openalex-snapshot
Silicon-level Solutions to Counteract Passive and Active Attacks
inferred← citeshttps://doi.org/10.1109/fpl.2008.4629925openalex-snapshot
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic
inferred← citeshttps://doi.org/10.1109/fpl.2012.6339147openalex-snapshot
On reconfigurable fabrics and generic side-channel countermeasures
inferred← citeshttps://doi.org/10.1109/fpl.2014.6927422openalex-snapshot
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security
inferred← citeshttps://doi.org/10.1109/hst.2008.4559042openalex-snapshot
Place-and-route impact on the security of DPL designs in FPGAs
inferred← citeshttps://doi.org/10.1109/icscs.2009.5412599openalex-snapshot
Overview of Dual rail with Precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors
inferred← citeshttps://doi.org/10.1109/mdt.2007.202openalex-snapshot
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
inferred← citeshttps://doi.org/10.1109/prime.2013.6603185openalex-snapshot
Simulated power analysis attacks on a DDPL crypto-core without routing constraints
inferred← citeshttps://doi.org/10.1109/reconfig.2009.50openalex-snapshot
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
inferred← citeshttps://doi.org/10.1109/s3s.2017.8309254openalex-snapshot
Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications
inferred← citeshttps://doi.org/10.1109/tc.2008.109openalex-snapshot
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
inferred← citeshttps://doi.org/10.1109/tc.2010.104openalex-snapshot
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
inferred← citeshttps://doi.org/10.1109/tc.2013.219openalex-snapshot
Automatic Application of Power Analysis Countermeasures
inferred← citeshttps://doi.org/10.1109/tcad.2015.2423274openalex-snapshot
A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation
inferred← citeshttps://doi.org/10.1109/tcsi.2018.2861738openalex-snapshot
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results
inferred← citeshttps://doi.org/10.1109/tcsi.2020.3005338openalex-snapshot
Ask Less, Get More: Side-Channel Signal Hiding, Revisited
inferred← citeshttps://doi.org/10.1145/1403375.1403685openalex-snapshot
Power balanced gates insensitive to routing capacitance mismatch
inferred← citeshttps://doi.org/10.1145/1857927.1857938openalex-snapshot
Evaluation of Random Delay Insertion against DPA on FPGAs
inferred← citeshttps://doi.org/10.1145/2024724.2024778openalex-snapshot
A first step towards automatic application of power analysis countermeasures
inferred← citeshttps://doi.org/10.1145/3194554.3194616openalex-snapshot
Physical Protection of Lattice-Based Cryptography
inferred← citeshttps://doi.org/10.1504/ijiei.2011.044101openalex-snapshot
Design and characterisation of an AES chip embedding countermeasures
inferred← citeshttps://doi.org/10.1587/transfun.e94.a.200openalex-snapshot
How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers
inferred← citeshttps://doi.org/10.1587/transfun.e95.a.234openalex-snapshot
Toward Effective Countermeasures against an Improved Fault Sensitivity Analysis
inferred← citeshttps://doi.org/10.3390/s24185894openalex-snapshot
Tiny Security Hole: First-Order Vulnerability of Masked SEED and Its Countermeasure
inferred← citeshttps://doi.org/10.48550/arxiv.0809.3942openalex-snapshot
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks
inferred← citeshttps://doi.org/10.5555/1870926.1871133openalex-snapshot
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
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