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Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/malq.19600060105openalex-snapshot
Weak Second‐Order Arithmetic and Finite Automata
inferredcites →https://doi.org/10.1006/inco.1993.1025openalex-snapshot
Real-Time Logics: Complexity and Expressiveness
inferredcites →https://doi.org/10.1007/3-540-46691-6_5openalex-snapshot
Product Interval Automata: A Subclass of Timed Automata
inferredcites →https://doi.org/10.1007/3-540-58468-4_191openalex-snapshot
Specifying timed state sequences in powerful decidable logics and timed automata
inferredcites →https://doi.org/10.1007/bf01995674openalex-snapshot
Specifying real-time properties with metric temporal logic
inferredcites →https://doi.org/10.1007/bfb0014711openalex-snapshot
State clock logic: A decidable real-time logic
inferredcites →https://doi.org/10.1016/b978-0-444-88074-1.50009-3openalex-snapshot
Automata on Infinite Objects
inferredcites →https://doi.org/10.1016/s0304-3975(97)00173-4openalex-snapshot
Event-clock automata: a determinizable class of timed automata
inferredcites →https://doi.org/10.1142/s0129054103001923openalex-snapshot
A Logical Characterisation of Event Clock Automata
inferredcites →https://doi.org/10.1145/112600.112613openalex-snapshot
The benefits of relaxing punctuality
inferredcites →https://doi.org/10.1145/567446.567462openalex-snapshot
On the temporal analysis of fairness
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