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Equivalence Checking of Digital Circuits: Fundamentals, Principles, Methods

https://doi.org/10.1007/b105298
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Introduction
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On Neural Network Equivalence Checking Using SMT Solvers
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Advanced Equivalence Checking for Quantum Circuits
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A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models
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Characteristics of reversible circuits for error detection
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Experimental Equivalence Checking of Quantum Circuits by Nonlocality
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Using Island Model in Asynchronous Evolutionary Strategy to Search for Backdoors for SAT
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Verification for Field-coupled Nanocomputing Circuits
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Approximate Equivalence Checking of Noisy Quantum Circuits
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Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters
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An Equivalence Checking Method for Circuits with Black Boxes Based on Logic Cone and SAT
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Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions
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Formally verifying an RTOS scheduling monitor IP core in embedded systems
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Formal equivalence checking between high-level and RTL hardware designs
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A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs
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Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS
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An equivalence checking algorithm based on cutset match of gate-level circuits
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MNT Designer: A Comprehensive Design Tool for Field-Coupled Nanocomputing
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Equivalence Checking of Sequential Quantum Circuits
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Deploying SEC for Design Cycle Time Reduction and Quality Improvement
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A Tensor Network based Decision Diagram for Representation of Quantum Circuits
inferred← citeshttps://doi.org/10.1145/3649329.3658496openalex-snapshot
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent
inferred← citeshttps://doi.org/10.11606/t.3.2014.tde-23122014-155143openalex-snapshot
Checagem de equivalência de sequências de estados de projetos digitais em RTL com modelos de referência em alto nível e de protocolo de comunicação.
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On Probabilistic Generalization of Backdoors in Boolean Satisfiability
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Probabilistic Generalization of Backdoor Trees with Application to SAT
inferred← citeshttps://doi.org/10.23919/date56975.2023.10137179openalex-snapshot
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
inferred← citeshttps://doi.org/10.23919/date58400.2024.10546556openalex-snapshot
Using Formal Verification Methods for Optimization of Circuits Under External Constraints
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Using Disjunctive Diagrams for Preprocessing of Conjunctive Normal Forms
inferred← citeshttps://doi.org/10.23919/mipro57284.2023.10159845openalex-snapshot
Speeding up the Solving of Logical Equivalence Checking Problems with Disjunctive Diagrams
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Karma: um ambiente para o aprendizado de síntese de funções Booleanas
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