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Formal Modeling and Analysis of Timed Systems: First International Workshop, FORMATS 2003, Marseille, France, September 6-7, 2003, Revised Papers
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/inco.1994.1045openalex-snapshot
Symbolic Model Checking for Real-Time Systems
inferredcites →https://doi.org/10.1006/inco.1995.1059openalex-snapshot
Timing Verification by Successive Approximation
inferredcites →https://doi.org/10.1007/3-540-45657-0_26openalex-snapshot
IF-2.0: A Validation Environment for Component-Based Real-Time Systems
inferredcites →https://doi.org/10.1007/3-540-48153-2_11openalex-snapshot
Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
inferredcites →https://doi.org/10.1007/3-540-49519-3_11openalex-snapshot
A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk
inferredcites →https://doi.org/10.1007/3-540-52148-8_17openalex-snapshot
Timing assumptions and verification of finite-state concurrent systems
inferredcites →https://doi.org/10.1007/3-540-54233-7_126openalex-snapshot
Safety for branching time semantics
inferredcites →https://doi.org/10.1007/3-540-60385-9_12openalex-snapshot
Timing analysis of asynchronous circuits using timed automata
inferredcites →https://doi.org/10.1007/3-540-61604-7_75openalex-snapshot
Verifying abstractions of timed systems
inferredcites →https://doi.org/10.1007/3-540-63166-6_19openalex-snapshot
Some progress in the symbolic verification of timed automata
inferredcites →https://doi.org/10.1007/3-540-63166-6_20openalex-snapshot
STARI: A case study in compositional and hierarchical timing verification
inferredcites →https://doi.org/10.1007/bfb0028779openalex-snapshot
Kronos: A model-checking tool for real-time systems
inferredcites →https://doi.org/10.1007/s100090050009openalex-snapshot
KRONOS: a verification tool for real-time systems
inferredcites →https://doi.org/10.1007/s100090050012openalex-snapshot
Protocol verification with the ALDÉBARAN toolset
inferredcites →https://doi.org/10.1109/async.2000.836774openalex-snapshot
Formal verification of safety properties in timed circuits
inferredcites →https://doi.org/10.1109/iccsse.1996.554845openalex-snapshot
Hardware timing verification using KRONOS
inferredcites →https://doi.org/10.1109/real.1996.563700openalex-snapshot
Approximate reachability analysis of timed automata
inferredcites →https://doi.org/10.1109/tcad.2003.816214openalex-snapshot
Modular verification of timed circuits using automatic abstraction
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Position paper on the challenges posed by modern applications to cyber-physical systems theory
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Symmetry reduction for time Petri net state classes
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Robust Testing for Cyber-Physical Systems using Reinforcement Learning
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Incorporating Logic in Online Preference Learning for Safe Personalization of Autonomous Vehicles
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Diagnosis of Labeled Time Petri Nets Using Time Interval Splitting
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