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On the models for asynchronous circuit behaviour with OR causality
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-07135-0_113openalex-snapshot
A fundamental theorem of asynchronous parallel computation
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Stable models of typed λ-calculi
inferredcites →https://doi.org/10.1007/3-540-08921-7_101openalex-snapshot
On the computational power of extended petri nets
inferredcites →https://doi.org/10.1007/3-540-19488-6_133openalex-snapshot
Computations, residuals, and the power of indeterminacy
inferredcites →https://doi.org/10.1007/978-1-4615-3212-5openalex-snapshot
Algorithms for Synthesis and Testing of Asynchronous Circuits
inferredcites →https://doi.org/10.1007/978-94-009-0487-3openalex-snapshot
Self-Timed Control of Concurrent Processes
inferredcites →https://doi.org/10.1007/bf01379149openalex-snapshot
Modeling concurrency with partial orders
inferredcites →https://doi.org/10.1007/bfb0022474openalex-snapshot
Petri nets, event structures and domains
inferredcites →https://doi.org/10.1007/bfb0032041openalex-snapshot
Stability and sequentiality in dataflow networks
inferredcites →https://doi.org/10.1016/0304-3975(77)90044-5openalex-snapshot
LCF considered as a programming language
inferredcites →https://doi.org/10.1016/0304-3975(81)90112-2openalex-snapshot
Petri nets, event structures and domains, part I
inferredcites →https://doi.org/10.1016/0378-4754(82)90066-0openalex-snapshot
Petri Net theory and the modeling of systems
inferredcites →https://doi.org/10.1016/s0167-9260(86)80002-5openalex-snapshot
On the models for designing VLSI asynchronous digital systems
inferredcites →https://doi.org/10.1049/ip-d.1993.0016openalex-snapshot
On designing controllers for a class of uncertain sampled-data nonlinear systems
inferredcites →https://doi.org/10.1049/ip-e.1993.0018openalex-snapshot
Event-driven logic (EDL) approach to digital systems representation and related design processes
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Introduction to V.L.S.I. Systems
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/43.177405openalex-snapshot
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
inferredcites →https://doi.org/10.1109/43.41504openalex-snapshot
Automatic synthesis of asynchronous circuits from high-level specifications
inferredcites →https://doi.org/10.1109/5.24143openalex-snapshot
Petri nets: Properties, analysis and applications
inferredcites →https://doi.org/10.1109/92.311648openalex-snapshot
A low latency asynchronous arbitration circuit
inferredcites →https://doi.org/10.1109/async.1994.656281openalex-snapshot
Bounded delay timing analysis of a class of CSP programs with choice
inferredcites →https://doi.org/10.1109/async.1994.656287openalex-snapshot
Verification of the speed-independent circuits by STG unfoldings
inferredcites →https://doi.org/10.1109/edac.1991.206389openalex-snapshot
Formal method for self-timed design
inferredcites →https://doi.org/10.1109/iccad.1990.129875openalex-snapshot
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
inferredcites →https://doi.org/10.1109/iccad.1991.185264openalex-snapshot
Automatic synthesis of locally-clocked asynchronous state machines
inferredcites →https://doi.org/10.1109/iccad.1992.279390openalex-snapshot
A unified signal transition graph model for asynchronous control circuit synthesis
inferredcites →https://doi.org/10.1109/iccd.1992.276208openalex-snapshot
Algorithms for interface timing verification
inferredcites →https://doi.org/10.1109/iccd.1992.276282openalex-snapshot
Sequential circuit design using synthesis and optimization
inferredcites →https://doi.org/10.1109/iccd.1992.276300openalex-snapshot
On limitations and extensions of STG model for designing asynchronous control circuits
inferredcites →https://doi.org/10.1109/iccd.1992.276302openalex-snapshot
Automatic synthesis and verification of hazard-free control circuits from asynchronous finite state machine specifications
inferredcites →https://doi.org/10.25405/ncl.34292163openalex-snapshot
Signal Graphs: from Self-Timed to Timed Ones
inferredcites →https://doi.org/10.5555/951513.951556openalex-snapshot
Formal method for self-timed design
inferredcites →https://doi.org/10.6100/ir272918openalex-snapshot
Translating programs into delay-insensitive circuits
inferredcites →https://doi.org/10.6100/ir372904openalex-snapshot
Handshake circuits : an intermediary between communicating processes and VLSI
inferredcites →https://doi.org/10.7907/b9wzv-xrc02openalex-snapshot
Synthesis of Asynchronous VLSI Circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Achieving a General, Formal and Decidable Approach to the OR-Join in Workflow Using Reset Nets
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Decomposition in Asynchronous Circuit Design
inferred← citeshttps://doi.org/10.1007/3-540-58152-9_31openalex-snapshot
OR causality: Modelling and hardware implementation
inferred← citeshttps://doi.org/10.1007/3-540-65307-4_49openalex-snapshot
Petri nets and digital hardware design
inferred← citeshttps://doi.org/10.1007/978-1-4757-3143-9_4openalex-snapshot
Properties of Change Diagrams
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Refinement of Actions for Real-Time Concurrent Systems with Causal Ambiguity
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Component Refinement and CSC Solving for STG Decomposition
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Workcraft: A Static Data Flow Structure Editing, Visualisation and Analysis Tool
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Elasticity and Petri Nets
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On the Origin of Events: Branching Cells as Stubborn Sets
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Maximal Confluent Processes
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Refinement of actions for real-time concurrent systems with causal ambiguity
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Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines
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Component refinement and CSC-solving for STG decomposition
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Asynchrony and persistence in reaction systems
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Towards power-elastic systems through concurrency management
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On process-algebraic verification of asynchronous circuits
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Output-Determinacy and Asynchronous Circuit Synthesis
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Time elastic digital systems and Petri Nets
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Improved Parallel Composition of Labelled Petri Nets
inferred← citeshttps://doi.org/10.1109/async.2003.1199176openalex-snapshot
Low-latency control structures with slack
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Redressing timing issues for speed-independent circuits in deep submicron age
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A New Design Technique for Weakly Indicating Function Blocks
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Functional approach in self-timed circuit design
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Performance analysis of concurrent systems with early evaluation
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An arbiter synthesis approach based on arbitration scheme generation/selection for HW/SW co-design
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An Eliminating Causal Ambiguity Approach to Reactive Systems
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On-line testing of globally asynchronous circuits
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Timing issues in system-level design
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Asynchronous Arbitration Primitives for New Generation of Circuits and Systems
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Towards action refinement for concurrent systems with causal ambiguity
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Towards action refinement for concurrent systems with causal ambiguity
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Arbitration schemes synthesis approach for multiprocessor systems
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Conditional Partial Order Graphs: Model, Synthesis, and Application
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Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip
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Automating the Design of Asynchronous Logic Control for AMS Electronics
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Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
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SYNCHRONIZATION AND CANCELATION IN WORKFLOWS BASED ON RESET NETS
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Performance analysis of concurrent systems with early evaluation
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Synchronous elastic circuits with early evaluation and token counterflow
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Rate derivation and its applications to reactive, real-time embedded systems
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Signal Transition Graphs for Asynchronous Data Path Circuits
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Complexity of Checking Output-Determinacy in General Petri Nets
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Quantitative and Qualitative Extensions of Event Structures
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