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AC strength of a pattern generator

https://doi.org/10.1007/bf00137249
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/test.1990.114046openalex-snapshot
Arrangement of latches in scan-path design to improve delay fault coverage
inferredcites →https://doi.org/10.5555/800262.809170openalex-snapshot
A logic design structure for LSI testability

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/bf00995314openalex-snapshot
Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults
inferred← citeshttps://doi.org/10.1023/a:1008219725676openalex-snapshot
Delay Test Generation: A Hardware Perspective
inferred← citeshttps://doi.org/10.1023/a:1008370019685openalex-snapshot
Distributed BIST Architecture to Combat Delay Faults
inferred← citeshttps://doi.org/10.1109/43.298042openalex-snapshot
Broad-side delay test
inferred← citeshttps://doi.org/10.1109/ats.1995.485339openalex-snapshot
Generator choices for delay test
inferred← citeshttps://doi.org/10.1109/ats.1998.741651openalex-snapshot
Exploiting BIST approach for two-pattern testing
inferred← citeshttps://doi.org/10.1109/dftvs.1994.630014openalex-snapshot
Augmenting scan path SRLs with an XOR network to enhance delay fault testing
inferred← citeshttps://doi.org/10.1109/glsv.1996.497636openalex-snapshot
An efficient multiple scan chain testing scheme
inferred← citeshttps://doi.org/10.1109/iccd.1999.808574openalex-snapshot
Design for testability to combat delay faults
inferred← citeshttps://doi.org/10.1109/iscas.1994.408757openalex-snapshot
Why cellular automata are better than LFSRs as built-in self-test generators for sequential-type faults
inferred← citeshttps://doi.org/10.1109/test.1997.639650openalex-snapshot
Scan latch design for delay test
inferred← citeshttps://doi.org/10.1109/vtest.1997.599448openalex-snapshot
An optimized BIST test pattern generator for delay testing
inferred← citeshttps://doi.org/10.1155/1993/81360openalex-snapshot
Built‐In Self‐Test: Milestones and Challenges
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