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WASP: A WSI Associative String Processor

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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4613-1621-3openalex-snapshot
Wafer Scale Integration
inferredcites →https://doi.org/10.1007/978-1-4613-1621-3_5openalex-snapshot
A WSI Image Processor
inferredcites →https://doi.org/10.1007/bf00932067openalex-snapshot
ASP modules: cost-effective building-blocks for real-time DSP systems
inferredcites →https://doi.org/10.1016/0168-9002(90)90145-vopenalex-snapshot
Fine-grain parallel computer architectures in future triggers
inferredcites →https://doi.org/10.1109/40.87518openalex-snapshot
ASP: a cost-effective parallel microcomputer
inferredcites →https://doi.org/10.1109/fmpc.1988.47408openalex-snapshot
Performance of the ASP on the DARPA architecture benchmark
inferredcites →https://doi.org/10.1109/icwsi.1990.63880openalex-snapshot
WASP: a wafer-scale massively parallel processor
inferredcites →https://doi.org/10.1109/icwsi.1990.63881openalex-snapshot
The WASP demonstrator programme: the engineering of a wafer-scale system
inferredcites →https://doi.org/10.1109/wafer.1989.47530openalex-snapshot
Future military avionics applications of wafer-scale technology
inferredcites →https://doi.org/10.1109/wafer.1989.47539openalex-snapshot
WASP: a WSI associative string processor
inferredcites →https://doi.org/10.1109/wafer.1989.47557openalex-snapshot
A 3D HDI ASP: a cost-effective alternative to WSI signal processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4899-1331-9_26openalex-snapshot
A Distributed Parallel Associative Processor (DPAP) for the Execution of Logic Programs
inferred← citeshttps://doi.org/10.1109/2.330041openalex-snapshot
An associative architecture for genetic algorithm-based machine learning
inferred← citeshttps://doi.org/10.1109/5.503299openalex-snapshot
A modular massively parallel computing approach to image-related processing
inferred← citeshttps://doi.org/10.1109/96.311781openalex-snapshot
3D-WASP devices for on-line signal and data processing
inferred← citeshttps://doi.org/10.1109/96.404097openalex-snapshot
Defect and fault tolerant interconnection strategies for WASP devices
inferred← citeshttps://doi.org/10.1109/96.407073openalex-snapshot
Seventh IEEE International Conference on Wafer Scale Integration
inferred← citeshttps://doi.org/10.1109/asap.1993.397177openalex-snapshot
A CAD tool for electromagnetic simulation on the associative string processor
inferred← citeshttps://doi.org/10.1109/empdp.1994.592521openalex-snapshot
An Implementation Of A Set Mode For Prolog On A Parallell Associative Processor
inferred← citeshttps://doi.org/10.1109/icecs.1996.584446openalex-snapshot
Associative memory neural networks for time series prediction
inferred← citeshttps://doi.org/10.1109/icnn.1995.487565openalex-snapshot
Evaluation of training and mapping Sigma-pi networks to a massively parallel processor
inferred← citeshttps://doi.org/10.1109/icwsi.1991.151712openalex-snapshot
Yield considerations in the design of WASP3
inferred← citeshttps://doi.org/10.1109/icwsi.1992.171800openalex-snapshot
A 3-D WASP module for real-time signal and data processing
inferred← citeshttps://doi.org/10.1109/icwsi.1992.171801openalex-snapshot
WASP 3: A real time signal and data processor
inferred← citeshttps://doi.org/10.1109/icwsi.1992.171802openalex-snapshot
The application of yield modelling to the WASP parallel processing architecture
inferred← citeshttps://doi.org/10.1109/icwsi.1992.171803openalex-snapshot
HASP-1002: a hybrid wafer scale associative string processor
inferred← citeshttps://doi.org/10.1109/icwsi.1995.515433openalex-snapshot
Wafer-scale embedded-MPC modules for cost-effective image processing systems
inferred← citeshttps://doi.org/10.1109/icwsi.1995.515454openalex-snapshot
An experimental fault-tolerant active substrate MPC MCM using standard gate array technology
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