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Minimal cost one-dimensional linear hybrid cellular automata of degree through 500

https://doi.org/10.1007/bf00993091
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf00137255openalex-snapshot
Primitive polynomials of degree 301 through 500
inferredcites →https://doi.org/10.1016/0167-9260(89)90009-6openalex-snapshot
Built-in test for VLSI: Pseudorandom techniques
inferredcites →https://doi.org/10.1017/cbo9781139172769openalex-snapshot
Introduction to Finite Fields and their Applications
inferredcites →https://doi.org/10.1049/el:19911016openalex-snapshot
Determination of minimal cost one-dimensional linear hybrid cellular automata
inferredcites →https://doi.org/10.1109/43.489103openalex-snapshot
Synthesis of one-dimensional linear hybrid cellular automata
inferredcites →https://doi.org/10.1109/43.55213openalex-snapshot
The analysis of one-dimensional linear cellular automata and their aliasing properties
inferredcites →https://doi.org/10.1109/iscas.1994.408757openalex-snapshot
Why cellular automata are better than LFSRs as built-in self-test generators for sequential-type faults

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Maximal Length Cellular Automata
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Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults
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On the Use of Cellular Automata in Symmetric Cryptography
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Design and synthesis of low power weighted random pattern generator considering peak power reduction
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Cycle structure of non-uniform cellular automata
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Implementation and Research on EHW-based Digital Chip Using Handel-C Language
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A New Particle Model For Prediction Coding of Lossless Data Compression
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A Compute-in-Memory Annealing Processor With Interaction Coefficient Reuse and Sparse Energy Computation for Solving Combinatorial Optimization Problems
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Implicit test pattern generation constrained to cellular automata embedding
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Transition maximization techniques for enhancing the two-pattern fault coverage of pseudorandom test pattern generators
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Low power BIST via non-linear hybrid cellular automata
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LAYERED CELLULAR AUTOMATA FOR PSEUDORANDOM NUMBER GENERATION
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A versatile FPGA-based high speed bit error rate testing scheme /
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