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On the capabilities of systolic systems

https://doi.org/10.1007/bf01187090
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4613-9323-8_14openalex-snapshot
A Systematic Design and Explanation of the Atrubin Multiplier
inferredcites →https://doi.org/10.1007/bf00289248openalex-snapshot
Iterative arrays with direct central control
inferredcites →https://doi.org/10.1007/bf01759032openalex-snapshot
Retiming synchronous circuitry
inferredcites →https://doi.org/10.1016/0012-365x(78)90011-0openalex-snapshot
A characterization of the minimum cycle mean in a digraph
inferredcites →https://doi.org/10.1016/s0022-0000(71)80013-2openalex-snapshot
Marked directed graphs
inferredcites →https://doi.org/10.1109/sfcs.1981.34openalex-snapshot
Optimizing synchronous systems
inferredcites →https://doi.org/10.1109/t-c.1969.222663openalex-snapshot
Real-Time Computation by n-Dimensional Iterative Arrays of Finite-State Machines
inferredcites →https://doi.org/10.1145/113379.113410openalex-snapshot
Understanding retiming through maximum average-weight cycles
inferredcites →https://doi.org/10.1147/rd.32.0114openalex-snapshot
Finite Automata and Their Decision Problems
inferredcites →https://doi.org/10.1184/r1/6608852openalex-snapshot
Recognize regular languages with programmable building-blocks

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11685654_14openalex-snapshot
On Teaching Fast Adder Designs: Revisiting Ladner & Fischer
inferred← citeshttps://doi.org/10.1007/3-540-49254-2_13openalex-snapshot
Deductive Hardware Design: A Functional Approach
inferred← citeshttps://doi.org/10.1007/3-540-60294-1_119openalex-snapshot
FPGA implementation of a rational adder
inferred← citeshttps://doi.org/10.1007/978-1-4613-9323-8_14openalex-snapshot
A Systematic Design and Explanation of the Atrubin Multiplier
inferred← citeshttps://doi.org/10.1016/0167-9260(95)00021-6openalex-snapshot
The Retiming Lemma: A simple proof and applications
inferred← citeshttps://doi.org/10.1016/s0167-9260(97)00003-5openalex-snapshot
A real-time systolic integer multiplier
inferred← citeshttps://doi.org/10.1016/s0167-9260(97)00017-5openalex-snapshot
Mirroring: a technique for pipelining semi-systolic and systolic arrays
inferred← citeshttps://doi.org/10.1016/s0167-9260(97)00028-xopenalex-snapshot
Overcoming chip-to-chip delays and clock skews
inferred← citeshttps://doi.org/10.1109/asap.1995.522932openalex-snapshot
Design of a systolic coprocessor for rational addition
inferred← citeshttps://doi.org/10.1109/asap.1996.542815openalex-snapshot
Overcoming chip-to-chip delays and clock skews
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