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A criterion for atomicity

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-51687-5_51openalex-snapshot
How to construct an atomic variable (extended abstract)
inferredcites →https://doi.org/10.1007/978-1-4612-4476-9_16openalex-snapshot
Serializable Programs, Parallelizable Assertions: A Basis for Interleaving
inferredcites →https://doi.org/10.1007/978-1-4757-3472-0_6openalex-snapshot
Towards a Theory of Parallel Programming
inferredcites →https://doi.org/10.1007/bf00268134openalex-snapshot
An axiomatic proof technique for parallel programs I
inferredcites →https://doi.org/10.1007/bf01786227openalex-snapshot
On interprocess communication
inferredcites →https://doi.org/10.1007/bf02280833openalex-snapshot
Multi-writer composite registers
inferredcites →https://doi.org/10.1007/bfb0019809openalex-snapshot
Atomic multireader register
inferredcites →https://doi.org/10.1007/bfb0022437openalex-snapshot
Pseudo read-modify-write operations: Bounded wait-free implementations
inferredcites →https://doi.org/10.1007/bfb0035779openalex-snapshot
How to share concurrent asynchronous wait-free variables
inferredcites →https://doi.org/10.1016/0167-6423(84)90003-0openalex-snapshot
Adequate proof principles for invariance and liveness properties of concurrent programs
inferredcites →https://doi.org/10.1109/12.9729openalex-snapshot
Constructing two-writer atomic registers
inferredcites →https://doi.org/10.1109/sfcs.1986.11openalex-snapshot
Atomic shared register access by asynchronous hardware
inferredcites →https://doi.org/10.1109/sfcs.1987.15openalex-snapshot
Concurrent reading while writing II: The multi-writer case
inferredcites →https://doi.org/10.1145/114005.102808openalex-snapshot
Wait-free synchronization
inferredcites →https://doi.org/10.1145/153724.153741openalex-snapshot
Atomic snapshots of shared memory
inferredcites →https://doi.org/10.1145/174652.174657openalex-snapshot
The elusive atomic register
inferredcites →https://doi.org/10.1145/2993.357247openalex-snapshot
The ``Hoare Logic'' of CSP, and All That
inferredcites →https://doi.org/10.1145/41840.41848openalex-snapshot
On processor coordination using asynchronous hardware
inferredcites →https://doi.org/10.1145/41840.41858openalex-snapshot
The elusive atomic register revisited
inferredcites →https://doi.org/10.1145/41840.41859openalex-snapshot
Constructing multi-reader atomic values from non-atomic values
inferredcites →https://doi.org/10.1145/41840.41860openalex-snapshot
A protocol for wait-free, atomic, multi-reader shared variables
inferredcites →https://doi.org/10.1145/48022.48024openalex-snapshot
Efficient synchronization of multiprocessors with shared memory
inferredcites →https://doi.org/10.1145/5001.5007openalex-snapshot
Axioms for memory access in asynchronous hardware systems
inferredcites →https://doi.org/10.1145/78969.78970openalex-snapshot
win and sin : predicate transformers for concurrency
inferredcites →https://doi.org/10.1145/78969.78972openalex-snapshot
Linearizability: a correctness condition for concurrent objects
inferredcites →https://doi.org/10.1145/93385.93394openalex-snapshot
Atomic snapshots of shared memory
inferredcites →https://doi.org/10.1145/93385.93396openalex-snapshot
Composite registers
inferredcites →https://doi.org/10.1145/97444.97701openalex-snapshot
Wait-free data structures in the asynchronous PRAM model
inferredcites →https://doi.org/10.21236/ada222765openalex-snapshot
Atomic Snapshots of Shared Memory

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-56188-9_21openalex-snapshot
The granularity of waiting (extended Abstract)
inferred← citeshttps://doi.org/10.1007/3-540-57271-6_26openalex-snapshot
Towards a necessary and sufficient condition for wait-free synchronization (Extended Abstract)
inferred← citeshttps://doi.org/10.1007/3-540-57271-6_27openalex-snapshot
Efficient algorithms for checking the atomicity of a run of read and write operations
inferred← citeshttps://doi.org/10.1007/bf01177745openalex-snapshot
Efficient algorithms for checking the atomicity of a run of read and write operations
inferred← citeshttps://doi.org/10.1007/bf02242703openalex-snapshot
Composite registers
inferred← citeshttps://doi.org/10.1007/bf02280833openalex-snapshot
Multi-writer composite registers
inferred← citeshttps://doi.org/10.1007/bfb0022437openalex-snapshot
Pseudo read-modify-write operations: Bounded wait-free implementations
inferred← citeshttps://doi.org/10.1007/s00165-004-0042-9openalex-snapshot
Ramifications of metastability in bit variables explored via Simpson’s 4-slot mechanism
inferred← citeshttps://doi.org/10.1007/s002360050010openalex-snapshot
Efficient algorithms for checking the atomicity of a run of read and write operations
inferred← citeshttps://doi.org/10.1016/0167-6423(92)90036-bopenalex-snapshot
Beyond atomic registers: bounded wait-free implementations of nontrivial objects
inferred← citeshttps://doi.org/10.1049/ip-cdt:19971218openalex-snapshot
New algorithms for asynchronous communication
inferred← citeshttps://doi.org/10.1049/ip-cdt:19971219openalex-snapshot
Role model analysis of an asynchronous communication mechanism
inferred← citeshttps://doi.org/10.1049/ip-cdt:20030419openalex-snapshot
Protocols for process interaction
inferred← citeshttps://doi.org/10.1049/ip-cdt:20040071openalex-snapshot
Freshness specification for a class of asynchronous communication mechanisms
inferred← citeshttps://doi.org/10.1049/ip-cdt:20045031openalex-snapshot
Data transfer analysis for a pair of asynchronous communication algorithms
inferred← citeshttps://doi.org/10.1109/emwrts.1998.684918openalex-snapshot
Asynchronous data sharing in multiprocessor real-time systems using process consensus
inferred← citeshttps://doi.org/10.1109/icdcsw.2003.1203552openalex-snapshot
A loop-free asynchronous data sharing mechanism in multiprocessor real-time systems based on timing properties
inferred← citeshttps://doi.org/10.1109/rtcsa.1999.811236openalex-snapshot
Loop-free asynchronous data sharing in multiprocessor real-time systems based on timing properties
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