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Formal analysis of correctness of behavioral transformations

https://doi.org/10.1007/bf01384133
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/0-387-97226-9_26openalex-snapshot
Behavior-preserving transformations for high-level synthesis
inferredcites →https://doi.org/10.1007/0-387-97226-9_27openalex-snapshot
From programs to transistors: Verifying hardware synthesis tools
inferredcites →https://doi.org/10.1007/3-540-10235-3openalex-snapshot
A Calculus of Communicating Systems
inferredcites →https://doi.org/10.1007/978-1-4615-4020-5_2openalex-snapshot
Calculus of Communicating Systems
inferredcites →https://doi.org/10.1007/bfb0012835openalex-snapshot
Computational metatheory in Nuprl
inferredcites →https://doi.org/10.1016/0167-7136(83)90174-9openalex-snapshot
IFIP 6th international symposium on computer hardware description languages and their applications
inferredcites →https://doi.org/10.1090/psapm/019/0235771openalex-snapshot
Assigning meanings to programs
inferredcites →https://doi.org/10.1109/43.39073openalex-snapshot
Behavioral transformation for algorithmic level IC design
inferredcites →https://doi.org/10.1109/dac.1978.1585173openalex-snapshot
A Technology-Relative Computer-Aided Design System: Abstract Representations, Transformations, and Design Tradeoffs
inferredcites →https://doi.org/10.1109/dac.1990.114855openalex-snapshot
How to prove the completeness of a set of register level design transformations
inferredcites →https://doi.org/10.1109/iccd.1991.139913openalex-snapshot
Illustration of the SFG-tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in Cathedral-II
inferredcites →https://doi.org/10.1109/iccd.1991.139915openalex-snapshot
A formally verified system for logic synthesis
inferredcites →https://doi.org/10.1109/mc.1983.1654268openalex-snapshot
Automatic Data Path Synthesis
inferredcites →https://doi.org/10.1109/tc.1981.6312154openalex-snapshot
Instruction set processor specifications (ISPS): The notation and its applications
inferredcites →https://doi.org/10.1109/tc.1983.1676294openalex-snapshot
An Abstract Model of Behavior for Hardware Descriptions
inferredcites →https://doi.org/10.1145/123186.123399openalex-snapshot
High-level synthesis
inferredcites →https://doi.org/10.1145/127601.127725openalex-snapshot
Industrial extensions to university high level synthesis tools
inferredcites →https://doi.org/10.1145/74382.74394openalex-snapshot
Architectural partitioning for system level design
inferredcites →https://doi.org/10.1145/74382.74456openalex-snapshot
Verification of hardware descriptions by retargetable code generation
inferredcites →https://doi.org/10.5555/285730.285785openalex-snapshot
The system architect's workbench
inferredcites →https://doi.org/10.5555/800095.803091openalex-snapshot
A Technology-Relative Computer-Aided Design System: Abstract Representations, Transformations, and Design Tradeoffs
inferredcites →https://doi.org/10.7907/zmy86-a1w29openalex-snapshot
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/047134608x.w1803openalex-snapshot
High Level Synthesis
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_15openalex-snapshot
Formal Synthesis at the Algorithmic Level
inferred← citeshttps://doi.org/10.1007/978-1-4419-9359-5_3openalex-snapshot
Related Work
inferred← citeshttps://doi.org/10.1016/s0065-2458(08)60545-8openalex-snapshot
Rapid Prototyping of Microelectronic Systems
inferred← citeshttps://doi.org/10.1109/aspdac.1995.486375openalex-snapshot
Correctness of transformations in high level synthesis
inferred← citeshttps://doi.org/10.1109/eurmic.1994.390401openalex-snapshot
A formal semantic model to fit SIL for transformational design
inferred← citeshttps://doi.org/10.1109/eurmic.1996.546380openalex-snapshot
A graph rewriting approach for transformational design of digital systems
inferred← citeshttps://doi.org/10.1109/hldvt.2000.889564openalex-snapshot
An approach to high-level synthesis system validation using formally verified transformations
inferred← citeshttps://doi.org/10.1109/isss.1995.520626openalex-snapshot
System level verification of video and image processing specifications
inferred← citeshttps://doi.org/10.1109/vlsisp.1994.574745openalex-snapshot
Verification of loop transformations for real time signal processing applications
inferred← citeshttps://doi.org/10.1145/224486.224533openalex-snapshot
System level verification of video and image processing specifications
inferred← citeshttps://doi.org/10.1145/233539.233541openalex-snapshot
From VHDL to efficient and first-time-right designs
inferred← citeshttps://doi.org/10.2197/ipsjtsldm.2.131openalex-snapshot
High-Level Verification
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