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Partitioning circuits for improved testability

https://doi.org/10.1007/bf01759033
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-95432-0_7openalex-snapshot
Optimizing Synchronous Circuitry by Retiming (Preliminary Version)
inferredcites →https://doi.org/10.1080/00401706.1961.10489978openalex-snapshot
Error Correcting Codes
inferredcites →https://doi.org/10.1109/jssc.1980.1051391openalex-snapshot
Built-in test for complex digital integrated circuits
inferredcites →https://doi.org/10.1109/sfcs.1981.34openalex-snapshot
Optimizing synchronous systems
inferredcites →https://doi.org/10.1109/tc.1980.1675641openalex-snapshot
Testing by Feedback Shift Register
inferredcites →https://doi.org/10.1109/tc.1981.1675717openalex-snapshot
Design for Autonomous Test
inferredcites →https://doi.org/10.1109/tc.1983.1676175openalex-snapshot
Exhaustive Test Pattern Generation with Constant Weight Vectors
inferredcites →https://doi.org/10.1109/tc.1983.1676202openalex-snapshot
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
inferredcites →https://doi.org/10.1145/800070.802178openalex-snapshot
The theory of signature testing for VLSI
inferredcites →https://doi.org/10.1147/rd.282.0212openalex-snapshot
Iterative Exhaustive Pattern Generation for Logic Testing
inferredcites →https://doi.org/10.2307/2003832openalex-snapshot
Error-Correcting Codes.
inferredcites →https://doi.org/10.5555/800262.809170openalex-snapshot
A logic design structure for LSI testability

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11685654_5openalex-snapshot
Parceling the Butterfly and the Batcher Sorting Network
inferred← citeshttps://doi.org/10.1007/978-3-322-85164-2_7openalex-snapshot
Literatur
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A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
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Cooperative multi-thread parallel tabu search with an application to circuit partitioning
inferred← citeshttps://doi.org/10.1016/0166-218x(94)00150-copenalex-snapshot
Graph partitioning applied to the logic testing of combinational circuits
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Minimal length test vectors for multiple-fault detection
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Automatic synthesis of testable VLSI cellular array multipliers
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Easily testable iterative logic arrays
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The pseudoexhaustive test of sequential circuits
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Optimizing resource utilization using transformations
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A method for pseudo-exhaustive test pattern generation
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A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits
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A timing-driven pseudoexhaustive testing for VLSI circuits
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Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets
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Low Power Pseudoexhaustive Testing with Cellular Automata
inferred← citeshttps://doi.org/10.1109/artcom.2009.145openalex-snapshot
Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing
inferred← citeshttps://doi.org/10.1109/cicc.1992.591300openalex-snapshot
Efficient Segmentation For Pseudo-exhaustive BIST
inferred← citeshttps://doi.org/10.1109/cicc.1994.379690openalex-snapshot
Circuit partitioning for pipelined pseudo-exhaustive testing using simulated annealing
inferred← citeshttps://doi.org/10.1109/ftcs.1989.105582openalex-snapshot
Pseudo-exhaustive test and segmentation: formal definitions and extended fault coverage results
inferred← citeshttps://doi.org/10.1109/iccd.1992.276289openalex-snapshot
On minimizing hardware overhead for pseudoexhaustive circuit testability
inferred← citeshttps://doi.org/10.1109/iscas.1988.15295openalex-snapshot
On partitioning for pseudo exhaustive testing of VLSI circuits
inferred← citeshttps://doi.org/10.1109/iscas.1992.229934openalex-snapshot
A metric towards efficient pseudo-exhaustive test pattern generation
inferred← citeshttps://doi.org/10.1109/iscas.2000.856416openalex-snapshot
A timing-driven pseudo-exhaustive testing of VLSI circuits
inferred← citeshttps://doi.org/10.1109/nrsc.2000.838953openalex-snapshot
An efficient algorithm to partition the combinational circuits for pseudoexhaustive testing
inferred← citeshttps://doi.org/10.1109/test.1988.207832openalex-snapshot
Reconfigurable hardware for pseudoexhaustive test
inferred← citeshttps://doi.org/10.1109/test.1989.82273openalex-snapshot
The pseudoexhaustive test of sequential circuits
inferred← citeshttps://doi.org/10.1109/test.1990.114118openalex-snapshot
Practical partitioning for testability with time-shared boundary scan
inferred← citeshttps://doi.org/10.1109/test.1993.470600openalex-snapshot
Multiconfiguration technique to reduce test duration for sequential circuits
inferred← citeshttps://doi.org/10.1109/test.1998.743170openalex-snapshot
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
inferred← citeshttps://doi.org/10.1145/157485.164880openalex-snapshot
An efficient partitioning strategy for pseudo-exhaustive testing
inferred← citeshttps://doi.org/10.1145/74382.74470openalex-snapshot
A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing
inferred← citeshttps://doi.org/10.31390/gradschool_dissertations.2087openalex-snapshot
Quiescent current testing of CMOS data converters
inferred← citeshttps://doi.org/10.48550/arxiv.1208.1814openalex-snapshot
On the Rank Number of Grid Graphs
inferred← citeshttps://doi.org/10.5555/949970.949974openalex-snapshot
Tools and devices supporting the pseudo-exhaustive test
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