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A lower bound on the area of permutation layouts

https://doi.org/10.1007/bf01759044
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/j.1538-7305.1964.tb04103.xopenalex-snapshot
Optimal Rearrangeable Multistage Connecting Networks
inferredcites →https://doi.org/10.1002/net.3230080308openalex-snapshot
Permutation layout
inferredcites →https://doi.org/10.1002/net.3230100208openalex-snapshot
Some comments on permutation layout
inferredcites →https://doi.org/10.1002/net.3230120307openalex-snapshot
Double‐row planar routing and permutation layout
inferredcites →https://doi.org/10.1007/978-1-4757-5927-3openalex-snapshot
Multiplicative Number Theory
inferredcites →https://doi.org/10.1007/bf01744433openalex-snapshot
New lower bound techniques for VLSI
inferredcites →https://doi.org/10.1007/bf01759038openalex-snapshot
Multilayer grid embeddings for VLSI
inferredcites →https://doi.org/10.1007/bf02126799openalex-snapshot
Ramanujan graphs
inferredcites →https://doi.org/10.1007/bf02579166openalex-snapshot
Eigenvalues and expanders
inferredcites →https://doi.org/10.1007/bf02579202openalex-snapshot
Expanding graphs contain all small trees
inferredcites →https://doi.org/10.1016/0012-365x(88)90189-6openalex-snapshot
Explicit construction of linear sized tolerant networks
inferredcites →https://doi.org/10.1016/0095-8956(85)90092-9openalex-snapshot
λ1, Isoperimetric inequalities for graphs, and superconcentrators
inferredcites →https://doi.org/10.1049/ip-i-1.1981.0010openalex-snapshot
Introduction to V.L.S.I. Systems
inferredcites →https://doi.org/10.1109/dac.1982.1585541openalex-snapshot
The "PI" (Placement And Interconnect) System
inferredcites →https://doi.org/10.1109/sfcs.1985.37openalex-snapshot
Multi-layer grid embeddings
inferredcites →https://doi.org/10.1109/tc.1981.6312176openalex-snapshot
Universality considerations in VLSI circuits
inferredcites →https://doi.org/10.1109/tcs.1976.1084169openalex-snapshot
The multilayer routing problem: Algorithms and necessary and sufficient conditions for the single-row, single-layer case
inferredcites →https://doi.org/10.1109/tcs.1977.1084323openalex-snapshot
Thickness of graphs with degree constrained vertices
inferredcites →https://doi.org/10.1109/tcs.1979.1084650openalex-snapshot
On optimum single-row routing
inferredcites →https://doi.org/10.1112/blms/2.1.105openalex-snapshot
MULTIPLICATIVE NUMBER THEORY
inferredcites →https://doi.org/10.1137/0136016openalex-snapshot
A Separator Theorem for Planar Graphs
inferredcites →https://doi.org/10.1137/0209046openalex-snapshot
Applications of a Planar Separator Theorem
inferredcites →https://doi.org/10.1137/0401009openalex-snapshot
Universal Chains and Wiring Layouts
inferredcites →https://doi.org/10.1145/12130.12154openalex-snapshot
Explicit expanders and the Ramanujan conjectures
inferredcites →https://doi.org/10.1184/r1/6714269openalex-snapshot
A Complexity Theory for VLSI
inferredcites →https://doi.org/10.5555/800263.809247openalex-snapshot
The "PI" (Placement And Interconnect) System

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-47738-1_30openalex-snapshot
3—Dimensional Single Active Layer Routing
inferred← citeshttps://doi.org/10.1007/3-540-52921-7_77openalex-snapshot
A tight lower bound on the size of planar permutation networks
inferred← citeshttps://doi.org/10.1007/bf01759038openalex-snapshot
Multilayer grid embeddings for VLSI
inferred← citeshttps://doi.org/10.1016/0304-3975(94)90135-xopenalex-snapshot
Shallow grates
inferred← citeshttps://doi.org/10.1016/j.dam.2006.05.010openalex-snapshot
Routing vertex disjoint Steiner-trees in a cubic grid and connections to VLSI
inferred← citeshttps://doi.org/10.1016/s0304-3975(97)00228-4openalex-snapshot
A partial k-arboretum of graphs with bounded treewidth
inferred← citeshttps://doi.org/10.1109/92.845901openalex-snapshot
Resource requirements and layouts for field programmable interconnection chips
inferred← citeshttps://doi.org/10.1109/icvd.1995.512142openalex-snapshot
Resource requirements for field programmable interconnection chips
inferred← citeshttps://doi.org/10.1137/0405045openalex-snapshot
A Tight Lower Bound on the Size of Planar Permutation Networks
inferred← citeshttps://doi.org/10.1137/s0097539796312733openalex-snapshot
Node-Disjoint Paths on the Mesh and a New Trade-Off in VLSI Layout
inferred← citeshttps://doi.org/10.1145/129712.129726openalex-snapshot
Fault tolerant planar communication networks
inferred← citeshttps://doi.org/10.1145/237814.238007openalex-snapshot
Node-disjoint paths on the mesh and a new trade-off in VLSI layout
inferred← citeshttps://doi.org/10.7916/d8zp45ktopenalex-snapshot
Unconditional Lower Bounds in Complexity Theory
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