On the public citation graph
Bus protocol conversion: From timing diagrams to state machines
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-10235-3openalex-snapshot
A Calculus of Communicating Systems
inferredcites →https://doi.org/10.1007/3-540-18625-5_46openalex-snapshot
Submodule construction as equation solving in CCS
inferredcites →https://doi.org/10.1007/978-3-642-82921-5_4openalex-snapshot
Notes on Communicating Sequential Systems
inferredcites →https://doi.org/10.1016/0304-3975(88)90030-8openalex-snapshot
A timed model for communicating sequential processes
inferredcites →https://doi.org/10.1145/3318.3322openalex-snapshot
CIRCAL and the representation of communication, concurrency, and time
inferredcites →https://doi.org/10.1145/357195.357196openalex-snapshot
On the Construction of Submodule Specifications and Communication Protocols
inferredcites →https://doi.org/10.1145/74382.74396openalex-snapshot
Automatic production of controller specifications from control and timing behavioral descriptions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_7openalex-snapshot
Efficient Decompositional Model Checking for Regular Timing Diagrams
inferred← citeshttps://doi.org/10.1007/3-540-57529-4_63openalex-snapshot
A graphic language based on timing diagrams
inferred← citeshttps://doi.org/10.1007/bf02745517openalex-snapshot
A graphic language based on timing diagrams
inferred← citeshttps://doi.org/10.1016/0165-6074(93)90198-topenalex-snapshot
Introducing structure into behavioural descriptions obtained from timing diagram specifications
inferred← citeshttps://doi.org/10.1109/aspdac.1995.486384openalex-snapshot
Transformation of timing diagram specifications into VHDL code
inferred← citeshttps://doi.org/10.1109/cicc.1998.694913openalex-snapshot
Synthesis of interface controllers from timing diagram specifications
inferred← citeshttps://doi.org/10.1109/edac.1993.386409openalex-snapshot
Specification and verification of system-level hardware designs using time diagrams
inferred← citeshttps://doi.org/10.1109/eurdac.1992.246314openalex-snapshot
An approach to multi-paradigm controller synthesis from timing diagram specifications
inferred← citeshttps://doi.org/10.1109/eurmic.1994.390403openalex-snapshot
High level synthesis based on formal methods
inferred← citeshttps://doi.org/10.1109/icm.1998.825579openalex-snapshot
Verificatiom of synchronous realizability of interfaces from timing diagram specifications
inferred← citeshttps://doi.org/10.26190/unsworks/22938openalex-snapshot
Modelling and programming embedded controllers with timed automata and synchronous languages
inferred← citeshttps://doi.org/10.5555/159754.161803openalex-snapshot
An approach to multi-paradigm controller synthesis from timing diagram specifications
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