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Removing ε-transitions in timed automata
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/inco.1994.1045openalex-snapshot
Symbolic Model Checking for Real-Time Systems
inferredcites →https://doi.org/10.1007/3-540-55179-4_37openalex-snapshot
Minimum and maximum delay problems in realtime systems
inferredcites →https://doi.org/10.1007/3-540-58179-0_39openalex-snapshot
A determinizable class of timed automata
inferredcites →https://doi.org/10.1007/3-540-58468-4_191openalex-snapshot
Specifying timed state sequences in powerful decidable logics and timed automata
inferredcites →https://doi.org/10.1007/3-540-60084-1_93openalex-snapshot
The expressive power of clocks
inferredcites →https://doi.org/10.1007/3-540-60922-9_22openalex-snapshot
On the power of non-observable actions in timed automata
inferredcites →https://doi.org/10.1007/bf00709157openalex-snapshot
Minimum and maximum delay problems in real-time systems
inferredcites →https://doi.org/10.1007/bfb0032042openalex-snapshot
Automata for modeling real-time systems
inferredcites →https://doi.org/10.1007/bfb0084802openalex-snapshot
Minimization of timed transition systems
inferredcites →https://doi.org/10.1016/0020-0190(95)00077-popenalex-snapshot
Untiming timed languages
inferredcites →https://doi.org/10.1016/0304-3975(94)90010-8openalex-snapshot
A theory of timed automata
inferredcites →https://doi.org/10.1109/cdc.1991.261658openalex-snapshot
The control of dense real-time discrete event systems
inferredcites →https://doi.org/10.1109/sfcs.1992.267774openalex-snapshot
Back to the future: towards a theory of timed regular languages
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-44618-4_12openalex-snapshot
The Impressive Power of Stopwatches
inferred← citeshttps://doi.org/10.1007/3-540-46691-6_4openalex-snapshot
Renaming Is Necessary in Timed Regular Expressions
inferred← citeshttps://doi.org/10.1007/978-3-319-22975-1_19openalex-snapshot
Bounded Determinization of Timed Automata with Silent Transitions
inferred← citeshttps://doi.org/10.1007/978-3-540-31848-4_6openalex-snapshot
Online Testing of Real-time Systems Using Uppaal
inferred← citeshttps://doi.org/10.1007/978-3-540-75563-0_40openalex-snapshot
Fine-Grained Compatibility and Replaceability Analysis of Timed Web Service Protocols
inferred← citeshttps://doi.org/10.1007/978-3-540-78917-8_3openalex-snapshot
Testing Real-Time Systems Using UPPAAL
inferred← citeshttps://doi.org/10.1007/978-3-642-05031-2_1openalex-snapshot
Testing Real-Time Systems Using TINA
inferred← citeshttps://doi.org/10.1007/bfb0029958openalex-snapshot
Accepting Zeno words without making time stand still
inferred← citeshttps://doi.org/10.1007/s10009-002-0094-1openalex-snapshot
Automated test generation from timed automata
inferred← citeshttps://doi.org/10.1007/s10703-022-00396-6openalex-snapshot
Equivalence checking and intersection of deterministic timed finite state machines
inferred← citeshttps://doi.org/10.1007/s11241-017-9271-xopenalex-snapshot
Bounded determinization of timed automata with silent transitions
inferred← citeshttps://doi.org/10.1016/s0020-0190(97)00217-2openalex-snapshot
Timed automata and recognizability
inferred← citeshttps://doi.org/10.1016/s0304-3975(02)00813-7openalex-snapshot
Automatic synthesis of a subclass of schedulers in timed systems
inferred← citeshttps://doi.org/10.1016/s1571-0661(05)80334-2openalex-snapshot
Automatic Synthesis of Schedulers in Timed Systems
inferred← citeshttps://doi.org/10.1109/aiccsa.2008.4493609openalex-snapshot
Test of preemptive real-time systems
inferred← citeshttps://doi.org/10.1109/ecbs.2005.41openalex-snapshot
From Requirements to Specifications
inferred← citeshttps://doi.org/10.4018/ijertcs.2013100101openalex-snapshot
Conformance Testing of Preemptive Real-Time Systems
inferred← citeshttps://doi.org/10.46298/.10342openalex-snapshot
Waiting Nets: State Classes and Taxonomy
inferred← citeshttps://doi.org/10.70675/48e3d1fbz6773z4afcz9cb8za12943935e0eopenalex-snapshot
Formal verification at design stage of diagnosis related properties for discrete event and real-time systems
inferred← citeshttps://doi.org/10.70675/5102e5e1zc5a3z454ezb76cz14a4520c0cb1openalex-snapshot
Using timed automata formalism for modeling and analyzing home care plans
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