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The methodology of modal constraints

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-51237-3_14openalex-snapshot

The use of static constructs in a model process logic

inferredcites →https://doi.org/10.1007/3-540-52148-8_19openalex-snapshot

Modal specifications

inferredcites →https://doi.org/10.1007/3-540-54233-7_136openalex-snapshot

CCS + time = an interleaving model for real time systems

inferredcites →https://doi.org/10.1007/3-540-60630-0_2openalex-snapshot

A constraint oriented proof methodology based on modal transition systems

inferredcites →https://doi.org/10.1007/bfb0017309openalex-snapshot

Concurrency and automata on infinite sequences

inferredcites →https://doi.org/10.1007/bfb0020979openalex-snapshot

Fischer's protocol revisited: A simple proof using modal constraints

inferredcites →https://doi.org/10.1016/0167-6423(93)90003-8openalex-snapshot

Generating data flow analysis algorithms from modal specifications

inferredcites →https://doi.org/10.1109/lics.1988.5119openalex-snapshot

A modal process logic

inferredcites →https://doi.org/10.1145/167088.167242openalex-snapshot

Parametric real-time reasoning

inferredcites →https://doi.org/10.1145/567067.567080openalex-snapshot

Automatic verification of finite state concurrent system using temporal logic specifications

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-40436-8_11openalex-snapshot

Assume-Guarantee Reasoning for Additive Hybrid Behaviour

inferred← citeshttps://doi.org/10.1007/978-3-319-63121-9_7openalex-snapshot

Property-Preserving Parallel Decomposition

inferred← citeshttps://doi.org/10.1007/bfb0024423openalex-snapshot

Formal Systems Specification

inferred← citeshttps://doi.org/10.1007/bfb0024438openalex-snapshot

Tackling the RPC-memory specification problem with I/O automata

inferred← citeshttps://doi.org/10.1109/iccd.2003.1240869openalex-snapshot

Verification of timed circuits with failure directed abstractions

inferred← citeshttps://doi.org/10.1109/tcad.2005.854638openalex-snapshot

Verification of timed circuits with failure-directed abstractions

inferred← citeshttps://doi.org/10.1109/tcad.2009.2035544openalex-snapshot

Compositional Reachability Analysis for Efficient Modular Verification of Asynchronous Designs

inferred← citeshttps://doi.org/10.1109/tse.2008.107openalex-snapshot

Synthesis of Partial Behavior Models from Properties and Scenarios

inferred← citeshttps://doi.org/10.1109/tse.2012.62openalex-snapshot

Synthesizing Modal Transition Systems from Triggered Scenarios

inferred← citeshttps://doi.org/10.1145/2089116.2089119openalex-snapshot

Weak Alphabet Merging of Partial Behavior Models

inferred← citeshttps://doi.org/10.25560/23804openalex-snapshot

Synthesis and distribution of modal transition systems from triggered scenarios

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