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Multidimensional periodic scheduling model and complexity

https://doi.org/10.1007/bfb0024706
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-0292-0_9openalex-snapshot
An Efficient Microcode-Compiler for Custom DSP-Processors
inferredcites →https://doi.org/10.1007/bf01407931openalex-snapshot
Dataflow analysis of array and scalar references
inferredcites →https://doi.org/10.1007/bfb0035103openalex-snapshot
Periodic multiprocessor scheduling
inferredcites →https://doi.org/10.1109/43.3169openalex-snapshot
Sehwa: a software package for synthesis of pipelines from behavioral specifications
inferredcites →https://doi.org/10.1109/43.402495openalex-snapshot
Improved force-directed scheduling in high-throughput digital signal processing
inferredcites →https://doi.org/10.1109/asap.1990.145440openalex-snapshot
Systolic array implementation of nested loop programs
inferredcites →https://doi.org/10.1109/edac.1991.206442openalex-snapshot
PHIDEO: a silicon compiler for high speed algorithms
inferredcites →https://doi.org/10.1109/edac.1992.205882openalex-snapshot
Modeling data flow and control flow for high level memory management
inferredcites →https://doi.org/10.1109/tc.1987.5009446openalex-snapshot
Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing
inferredcites →https://doi.org/10.1145/125826.125848openalex-snapshot
The Omega test: a fast and practical integer programming algorithm for dependence analysis
inferredcites →https://doi.org/10.1145/74382.74385openalex-snapshot
A scheduling and resource allocation algorithm for hierarchical signal flow graphs
inferredcites →https://doi.org/10.5555/951513.951608openalex-snapshot
PHIDEO: a silicon compiler for high speed algorithms
inferredcites →https://doi.org/10.6100/ir450513openalex-snapshot
Multidimensional periodic scheduling

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/43.952736openalex-snapshot
A two-stage solution approach to multidimensional periodic scheduling
inferred← citeshttps://doi.org/10.1109/dac.2005.193876openalex-snapshot
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
inferred← citeshttps://doi.org/10.1109/edtc.1997.582402openalex-snapshot
Multidimensional periodic scheduling: a solution approach
inferred← citeshttps://doi.org/10.1109/isss.1997.621678openalex-snapshot
Fast and extensive system-level memory exploration for ATM applications
inferred← citeshttps://doi.org/10.1109/isss.2000.874028openalex-snapshot
Scheduling coarse-grain operations for VLIW processors
inferred← citeshttps://doi.org/10.1109/isss.2000.874051openalex-snapshot
Mapping array communication onto FIFO communication - towards an implementation
inferred← citeshttps://doi.org/10.1145/1065579.1065729openalex-snapshot
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
inferred← citeshttps://doi.org/10.1145/375977.375978openalex-snapshot
Data and memory optimization techniques for embedded systems
inferred← citeshttps://doi.org/10.5555/261693.261714openalex-snapshot
Fast and extensive system-level memory exploration for ATM applications
inferred← citeshttps://doi.org/10.5555/501790.501834openalex-snapshot
Mapping array communication onto FIFO communication - towards an implementation
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