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Verification of timed systems using POSETs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-52148-8_17openalex-snapshot
Timing assumptions and verification of finite-state concurrent systems
inferredcites →https://doi.org/10.1007/3-540-56496-9_14openalex-snapshot
Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits
inferredcites →https://doi.org/10.1007/3-540-56922-7_27openalex-snapshot
Efficient verification of parallel real-time systems
inferredcites →https://doi.org/10.1007/3-540-58179-0_76openalex-snapshot
Automatic verification of timed circuits
inferredcites →https://doi.org/10.1007/3-540-63166-6_19openalex-snapshot
Some progress in the symbolic verification of timed automata
inferredcites →https://doi.org/10.1007/3-540-63166-6_20openalex-snapshot
STARI: A case study in compositional and hierarchical timing verification
inferredcites →https://doi.org/10.1007/bf00709154openalex-snapshot
A stubborn attack on state explosion
inferredcites →https://doi.org/10.1007/bfb0023731openalex-snapshot
Using partial orders to improve automatic verification methods
inferredcites →https://doi.org/10.1023/a:1008682131325openalex-snapshot
Efficient Verification of Parallel Real–Time Systems
inferredcites →https://doi.org/10.1109/32.75415openalex-snapshot
Modeling and verification of time dependent systems using time Petri nets
inferredcites →https://doi.org/10.1109/arvlsi.1995.515610openalex-snapshot
Automatic synthesis of gate-level timed circuits with choice
inferredcites →https://doi.org/10.1109/async.1997.587166openalex-snapshot
Efficient timing analysis algorithms for timed state space exploration
inferredcites →https://doi.org/10.1109/iccd.1989.63357openalex-snapshot
Modelling timing assumption with trace theory
inferredcites →https://doi.org/10.1109/tcom.1976.1093424openalex-snapshot
Recoverability of Communication Protocols--Implications of a Theoretical Study
inferredcites →https://doi.org/10.1145/240518.240529openalex-snapshot
Efficient partial enumeration for timing analysis of asynchronous systems
inferredcites →https://doi.org/10.1145/240518.240530openalex-snapshot
Verification of asynchronous circuits using time Petri net unfolding
inferredcites →https://doi.org/10.5555/259794.259819openalex-snapshot
Practical applications of an efficient time separation of events algorithm
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/10722167_47openalex-snapshot
VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits
inferred← citeshttps://doi.org/10.1007/11867340_21openalex-snapshot
Adding Invariants to Event Zone Automata
inferred← citeshttps://doi.org/10.1007/11901914_24openalex-snapshot
Symbolic Unfoldings for Networks of Timed Automata
inferred← citeshttps://doi.org/10.1007/3-540-36190-1_8openalex-snapshot
Timed Verification of Asynchronous Circuits
inferred← citeshttps://doi.org/10.1007/3-540-36190-1_9openalex-snapshot
Performance Analysis of Asynchronous Circuits Using Markov Chains
inferred← citeshttps://doi.org/10.1007/3-540-44585-4_16openalex-snapshot
Automatic Abstraction for Verification of Timed Circuits and Systems?
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_11openalex-snapshot
Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
inferred← citeshttps://doi.org/10.1007/3-540-48320-9_30openalex-snapshot
Partial Order Reduction for Model Checking of Timed Automata
inferred← citeshttps://doi.org/10.1007/3-540-49253-4_7openalex-snapshot
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
inferred← citeshttps://doi.org/10.1007/978-0-387-35498-9_33openalex-snapshot
Verification of Abstracted Instruction Cache of TITAC2: A Case Study
inferred← citeshttps://doi.org/10.1007/978-3-540-30476-0_28openalex-snapshot
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
inferred← citeshttps://doi.org/10.1007/s00446-011-0151-7openalex-snapshot
Reconciling fault-tolerant distributed computing and systems-on-chip
inferred← citeshttps://doi.org/10.1016/j.tcs.2005.07.023openalex-snapshot
A partial order semantics approach to the clock explosion problem of timed automata
inferred← citeshttps://doi.org/10.1016/s1567-8326(02)00023-1openalex-snapshot
Symbolic model checking of timed guarded commands using difference decision diagrams
inferred← citeshttps://doi.org/10.1016/s1571-0661(04)80468-7openalex-snapshot
Verification of Asynchronous Circuits using Timed Automata
inferred← citeshttps://doi.org/10.1016/s1571-0661(04)80671-6openalex-snapshot
Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams1 1This work was carried out while the authors were at the Department of Information Technology, Technical University of Denmark, and was finnancially supported by a grant from the Danish Technical Research Council.
inferred← citeshttps://doi.org/10.1023/a:1011235419951openalex-snapshot
Automatic Real-Time Analysis of Reactive Systems with the PARTS Toolset
inferred← citeshttps://doi.org/10.1093/ietisy/e88-d.7.1646openalex-snapshot
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
inferred← citeshttps://doi.org/10.1109/4.902762openalex-snapshot
An asynchronous instruction length decoder
inferred← citeshttps://doi.org/10.1109/43.771173openalex-snapshot
Accelerating Markovian analysis of asynchronous systems using state compression
inferred← citeshttps://doi.org/10.1109/43.905681openalex-snapshot
Timed circuit verification using TEL structures
inferred← citeshttps://doi.org/10.1109/aspdac.2001.913329openalex-snapshot
Timed circuits: a new paradigm for high-speed design
inferred← citeshttps://doi.org/10.1109/aspdac.2001.913330openalex-snapshot
Conformance and mirroring for timed asynchronous circuits
inferred← citeshttps://doi.org/10.1109/async.1999.761518openalex-snapshot
Verification of delayed-reset domino circuits using ATACS
inferred← citeshttps://doi.org/10.1109/async.1999.761523openalex-snapshot
RAPPID: an asynchronous instruction length decoder
inferred← citeshttps://doi.org/10.1109/async.1999.761526openalex-snapshot
Bounding average time separations of events in stochastic timed Petri nets with choice
inferred← citeshttps://doi.org/10.1109/async.1999.761527openalex-snapshot
Timed trace theoretic verification using partial order reduction
inferred← citeshttps://doi.org/10.1109/async.2000.836774openalex-snapshot
Formal verification of safety properties in timed circuits
inferred← citeshttps://doi.org/10.1109/async.2002.1000302openalex-snapshot
Relative timing based verification of timed circuits and systems
inferred← citeshttps://doi.org/10.1109/edcc.2010.35openalex-snapshot
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining
inferred← citeshttps://doi.org/10.1109/icvd.1999.745146openalex-snapshot
Timed circuit synthesis using implicit methods
inferred← citeshttps://doi.org/10.1109/iscas.2000.856286openalex-snapshot
Stochastic cycle period analysis in timed circuits
inferred← citeshttps://doi.org/10.1109/prdc.2002.1185640openalex-snapshot
Level oriented formal model for asynchronous circuit verification and its efficient analysis method
inferred← citeshttps://doi.org/10.1145/370155.370387openalex-snapshot
Conformance and mirroring for timed asychronous circuits
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