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Systolic automata — power, characterizations, nonhomogeneity

https://doi.org/10.1007/bfb0030288
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4612-6264-0openalex-snapshot
Automata-Theoretic Aspects of Formal Power Series
inferredcites →https://doi.org/10.1007/bf00264617openalex-snapshot
On real-time cellular automata and trellis automata
inferredcites →https://doi.org/10.1007/bf00289240openalex-snapshot
A characterization of systolic binary tree automata and applications
inferredcites →https://doi.org/10.1007/bf00289573openalex-snapshot
Systolic automata for VLSI on balanced trees
inferredcites →https://doi.org/10.1016/0304-3975(83)90032-4openalex-snapshot
On a family of L languages resulting from systolic tree automata
inferredcites →https://doi.org/10.1016/0304-3975(83)90146-9openalex-snapshot
Systolic trees and systolic language recognition by tree automata
inferredcites →https://doi.org/10.1016/0304-3975(84)90015-xopenalex-snapshot
Characterizations and computational complexity of systolic trellis automata
inferredcites →https://doi.org/10.1051/ita/1984180100531openalex-snapshot
Systolic tree acceptors
inferredcites →https://doi.org/10.1051/ita/1984180403071openalex-snapshot
On real time and linear time cellular automata
inferredcites →https://doi.org/10.1080/00207168308803390openalex-snapshot
Programmable finite automata for VLSI†
inferredcites →https://doi.org/10.1109/mc.1982.1653825openalex-snapshot
Why systolic architectures?
inferredcites →https://doi.org/10.1109/t-c.1969.222663openalex-snapshot
Real-Time Computation by n-Dimensional Iterative Arrays of Finite-State Machines
inferredcites →https://doi.org/10.1145/300307.1040360openalex-snapshot
Elements of the Theory of Computation
inferredcites →https://doi.org/10.1145/800220.806704openalex-snapshot
Folding and unrolling systolic arrays (Preliminary Version)
inferredcites →https://doi.org/10.7551/mitpress/3999.001.0001openalex-snapshot
Iterative Arrays of Logical Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-19488-6_121openalex-snapshot
Systolic architectures, systems and computations
inferred← citeshttps://doi.org/10.1007/3-540-50647-0_112openalex-snapshot
Basic research for cellular processing
inferred← citeshttps://doi.org/10.1007/3-540-51498-8_26openalex-snapshot
Semilinear real-time systolic trellis automata
inferred← citeshttps://doi.org/10.1007/3-540-54345-7_54openalex-snapshot
Generating words by cellular automata
inferred← citeshttps://doi.org/10.1007/3-540-55808-x_9openalex-snapshot
Weak parallel machines: A new class of physically feasible parallel machine models
inferred← citeshttps://doi.org/10.1007/3540185356_27openalex-snapshot
Lower bound techniques for VLSI algorithms
inferred← citeshttps://doi.org/10.1007/bf01185564openalex-snapshot
Classes of systolic Y-tree automata and a comparison with systolic trellis automata
inferred← citeshttps://doi.org/10.1007/bf01191895openalex-snapshot
Languages accepted by systolic Y-tree automata: structural characterizations
inferred← citeshttps://doi.org/10.1007/bfb0016271openalex-snapshot
Undecidable problems concerning generalized pascal triangles of commutative algebras
inferred← citeshttps://doi.org/10.1007/bfb0029616openalex-snapshot
Comparisons among classes of Y-tree systolic automata
inferred← citeshttps://doi.org/10.1016/0304-3975(91)90277-9openalex-snapshot
Nonacceptability criteria and closure properties for the class of languages accepted by binary systolic tree automata
inferred← citeshttps://doi.org/10.1016/b978-0-444-88071-0.50006-0openalex-snapshot
Machine Models and Simulations
inferred← citeshttps://doi.org/10.1109/cmpeur.1989.93458openalex-snapshot
Broadcast-bus elimination without any loss of time efficiency in iterative (cellular or systolic) arrays
inferred← citeshttps://doi.org/10.4064/-28-1-125-134openalex-snapshot
Generalized pascal triangles: overview of new results
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