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Formal specification and verification of VHDL

https://doi.org/10.1007/bfb0031818
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4612-2704-5openalex-snapshot
Larch: Languages and Tools for Formal Specification
inferredcites →https://doi.org/10.1007/978-1-4615-2237-9openalex-snapshot
Formal Semantics for VHDL
inferredcites →https://doi.org/10.1109/32.58790openalex-snapshot
Formal verification of Ada programs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-0-387-35198-8_28openalex-snapshot
A Two-Level Approach to Automated Conformance Testing of VHDL Designs
inferred← citeshttps://doi.org/10.1007/bfb0028729openalex-snapshot
Transforming the theorem prover into a digital design tool: From concept car to off-road vehicle
inferred← citeshttps://doi.org/10.1007/bfb0054262openalex-snapshot
ACL2 support for verification projects
inferred← citeshttps://doi.org/10.1023/a:1008693709419openalex-snapshot
Formal Methods Technology Transfer: A View from NASA
inferred← citeshttps://doi.org/10.1023/a:1011217102270openalex-snapshot
Efficient Simulation of Formal Processor Models
inferred← citeshttps://doi.org/10.1109/date.1998.655865openalex-snapshot
Formal specification in VHDL for hardware verification
inferred← citeshttps://doi.org/10.1109/iscas.1998.705272openalex-snapshot
On the algebraic reuse of hardware design
inferred← citeshttps://doi.org/10.1109/tst.2015.7085635openalex-snapshot
Deadlock detection in FPGA design: A practical approach
inferred← citeshttps://doi.org/10.3990/1.9789090130866openalex-snapshot
Analysing industrial protocols with formal methods
inferred← citeshttps://doi.org/10.5555/368058.368142openalex-snapshot
Formal specification in VHDL for hardware verification
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