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Decomposition techniques for efficient ROBDD construction

https://doi.org/10.1007/bfb0031825
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/j.1538-7305.1959.tb01585.xopenalex-snapshot
Representation of Switching Circuits by Binary-Decision Programs
inferredcites →https://doi.org/10.1007/3-540-52148-8_30openalex-snapshot
Verification of synchronous sequential machines based on symbolic execution
inferredcites →https://doi.org/10.1007/3-540-61474-5_93openalex-snapshot
Symbolic model checking
inferredcites →https://doi.org/10.1007/978-1-4615-3190-6openalex-snapshot
Symbolic Model Checking
inferredcites →https://doi.org/10.1007/978-1-4615-3190-6_3openalex-snapshot
Symbolic Model Checking
inferredcites →https://doi.org/10.1007/bf00464357openalex-snapshot
Probabilistic verification of Boolean functions
inferredcites →https://doi.org/10.1109/12.644298openalex-snapshot
Indexed BDDs: algorithmic advances in techniques to represent and verify Boolean functions
inferredcites →https://doi.org/10.1109/43.631208openalex-snapshot
Symbolic FSM traversals based on the transition relation
inferredcites →https://doi.org/10.1109/43.85742openalex-snapshot
Circuit width, register allocation, and ordered binary decision diagrams
inferredcites →https://doi.org/10.1109/iccad.1988.122450openalex-snapshot
Evaluation and improvement of Boolean comparison method based on binary decision diagrams
inferredcites →https://doi.org/10.1109/iccad.1988.122451openalex-snapshot
Logic verification using binary decision diagrams in a logic synthesis environment
inferredcites →https://doi.org/10.1109/iccad.1990.129860openalex-snapshot
Implicit state enumeration of finite state machines using BDD's
inferredcites →https://doi.org/10.1109/iccad.1991.185305openalex-snapshot
Extended BDD's: trading off canonicity for structure in verification algorithms
inferredcites →https://doi.org/10.1109/iccad.1996.569909openalex-snapshot
Partitioned ROBDDs-a compact, canonical and efficiently manipulable representation for Boolean functions
inferredcites →https://doi.org/10.1109/icvd.1996.489494openalex-snapshot
A study of composition schemes for mixed apply/compose based construction of ROBDDs
inferredcites →https://doi.org/10.1109/tc.1978.1675141openalex-snapshot
Binary Decision Diagrams
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/123186.123222openalex-snapshot
Efficient implementation of a BDD package
inferredcites →https://doi.org/10.1145/136035.136043openalex-snapshot
Symbolic Boolean manipulation with ordered binary-decision diagrams
inferredcites →https://doi.org/10.1145/196244.196380openalex-snapshot
Auxiliary variables for extending symbolic traversal techniques to data paths
inferredcites →https://doi.org/10.1145/357062.357071openalex-snapshot
A fast algorithm for finding dominators in a flowgraph
inferredcites →https://doi.org/10.5555/244522.244894openalex-snapshot
Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions
inferredcites →https://doi.org/10.5555/259794.259802openalex-snapshot
Dynamic variable ordering for ordered binary decision diagrams

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-28916-3_11openalex-snapshot
Start Small But Dream Big: On Choosing a Static Variable Order for Multiplier BDDs
inferred← citeshttps://doi.org/10.1007/978-3-642-05356-6_6openalex-snapshot
Hardware-Verifikation
inferred← citeshttps://doi.org/10.1109/12.966501openalex-snapshot
A note on complexity of OBDD composition and efficiency of partitioned-OBDDs over OBDDs
inferred← citeshttps://doi.org/10.1109/43.806801openalex-snapshot
An efficient filter-based approach for combinational verification
inferred← citeshttps://doi.org/10.1109/iccad.1997.643565openalex-snapshot
Reachability analysis using partitioned-ROBDDs
inferred← citeshttps://doi.org/10.1109/iccad.1997.643609openalex-snapshot
Logic synthesis for large pass transistor circuits
inferred← citeshttps://doi.org/10.1109/icvd.1999.745188openalex-snapshot
Efficient scheduling techniques for ROBDD construction
inferred← citeshttps://doi.org/10.1109/iedec.2012.6186924openalex-snapshot
Learning CMOS logic gate design by exploring switch network domain
inferred← citeshttps://doi.org/10.1109/l-ca.2006.17openalex-snapshot
A Case for Compressing Traces with BDDs
inferred← citeshttps://doi.org/10.1109/mesiicon55227.2022.10093493openalex-snapshot
Monitoring the Effects of Static Variable Orders on the Construction of BDDs
inferred← citeshttps://doi.org/10.1145/1837274.1837334openalex-snapshot
Towards scalable system-level reliability analysis
inferred← citeshttps://doi.org/10.1145/263764.263784openalex-snapshot
Parallel breadth-first BDD construction
inferred← citeshttps://doi.org/10.1145/293625.293626openalex-snapshot
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
inferred← citeshttps://doi.org/10.1145/307418.307475openalex-snapshot
An efficient filter-based approach for combinational verification
inferred← citeshttps://doi.org/10.1145/337292.337613openalex-snapshot
Analysis of composition complexity and how to obtain smaller canonical graphs
inferred← citeshttps://doi.org/10.1527/tjsai.25.475openalex-snapshot
Propositionalizing the EM algorithm by BDDs
inferred← citeshttps://doi.org/10.23919/date58400.2024.10546775openalex-snapshot
Polynomial Formal Verification of Sequential Circuits
inferred← citeshttps://doi.org/10.5555/244522.244894openalex-snapshot
Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions
inferred← citeshttps://doi.org/10.5555/266388.266400openalex-snapshot
PHDD: an efficient graph representation for floating point circuit verification
inferred← citeshttps://doi.org/10.5555/266388.266513openalex-snapshot
Reachability analysis using partitioned-ROBDDs
inferred← citeshttps://doi.org/10.5555/266388.266604openalex-snapshot
Logic synthesis for large pass transistor circuits
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