On the public citation graph

A multi-grain parallelizing compilation scheme for OSCAR (optimally scheduled advanced multiprocessor)

https://doi.org/10.1007/bfb0038671
0 signed · 66 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/scj.4690221203openalex-snapshot
Coarse grain parallelism detection scheme of a fortran program
inferredcites →https://doi.org/10.1007/978-1-4613-1077-8openalex-snapshot
Parallel Programming and Compilers
inferredcites →https://doi.org/10.1007/978-1-4684-6894-6openalex-snapshot
Dependence Analysis for Supercomputing
inferredcites →https://doi.org/10.1007/bfb0038663openalex-snapshot
Optimization of data/control conditions in task graphs
inferredcites →https://doi.org/10.1109/12.2247openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1109/12.40844openalex-snapshot
The nonuniform distribution of instruction-level and machine parallelism and its effect on performance
inferredcites →https://doi.org/10.1109/52.1992openalex-snapshot
Multiprocessor synchronization for concurrent loops
inferredcites →https://doi.org/10.1109/mc.1984.1659185openalex-snapshot
The VLIW Machine: A Multiprocessor for Compiling Scientific Code
inferredcites →https://doi.org/10.1109/superc.1990.130111openalex-snapshot
Parallel processing of near fine grain tasks using static scheduling on OSCAR (optimally scheduled advanced multiprocessor)
inferredcites →https://doi.org/10.1109/tc.1980.1675676openalex-snapshot
High-Speed Multiprocessors and Compilation Techniques
inferredcites →https://doi.org/10.1109/tc.1984.1676371openalex-snapshot
Measuring the Parallelism Available for Very Long Instruction Word Architectures
inferredcites →https://doi.org/10.1109/tc.1984.1676376openalex-snapshot
Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing
inferredcites →https://doi.org/10.1109/tc.1987.5009495openalex-snapshot
Guided Self-Scheduling: A Practical Scheduling Scheme for Parallel Supercomputers
inferredcites →https://doi.org/10.1126/science.231.4741.967openalex-snapshot
Parallel Supercomputing Today and the Cedar Approach
inferredcites →https://doi.org/10.1137/0219051openalex-snapshot
Scheduling Sequential Loops on Parallel Processors
inferredcites →https://doi.org/10.1145/12276.13328openalex-snapshot
Interprocedural dependence analysis and parallelization
inferredcites →https://doi.org/10.1145/24039.24041openalex-snapshot
The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/321556.321565openalex-snapshot
Symbolic Generation of an Optimal Crout Algorithm for Sparse Systems of Linear Equations
inferredcites →https://doi.org/10.1145/321992.321999openalex-snapshot
An Algorithm for Structuring Flowgraphs
inferredcites →https://doi.org/10.1145/36204.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1145/55364.55385openalex-snapshot
A framework for determining useful parallelism
inferredcites →https://doi.org/10.1145/73141.74845openalex-snapshot
Determining average program execution times and their variance
inferredcites →https://doi.org/10.1145/7902.7904openalex-snapshot
Advanced compiler optimizations for supercomputers
inferredcites →https://doi.org/10.1145/989393.989411openalex-snapshot
Interprocedural dependence analysis and parallelization
inferredcites →https://doi.org/10.5555/110382.110617openalex-snapshot
Parallel processing of near fine grain tasks using static scheduling on OSCAR (optimally scheduled advanced multiprocessor)

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/jos.116openalex-snapshot
A standard task graph set for fair evaluation of multiprocessor scheduling algorithms
inferred← citeshttps://doi.org/10.1006/jpdc.2000.1712openalex-snapshot
The Shared Control Parallel Architecture Model
inferred← citeshttps://doi.org/10.1007/11596110_3openalex-snapshot
Hierarchical Parallelism Control for Multigrain Parallel Processing
inferred← citeshttps://doi.org/10.1007/3-540-39999-2_43openalex-snapshot
Coarse-grain Task Parallel Processing Using the OpenMP Backend of the OSCAR Multigrain Parallelizing Compiler
inferred← citeshttps://doi.org/10.1007/3-540-45574-4_13openalex-snapshot
Automatic Coarse Grain Task Parallel Processing on SMP Using OpenMP
inferred← citeshttps://doi.org/10.1007/3-540-47847-7_44openalex-snapshot
Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP
inferred← citeshttps://doi.org/10.1007/978-3-030-72789-5_1openalex-snapshot
Performance of Static and Dynamic Task Scheduling for Real-Time Engine Control System on Embedded Multicore Processor
inferred← citeshttps://doi.org/10.1007/978-3-031-31445-2_9openalex-snapshot
Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler
inferred← citeshttps://doi.org/10.1007/978-3-032-02436-7_7openalex-snapshot
Automatic Deep Learning Parallelization for Vector Multicore Chips with the OSCAR Parallelizing and the TVM Open-Source Deep Learning Compiler
inferred← citeshttps://doi.org/10.1007/978-3-319-52709-3_21openalex-snapshot
Automatic Local Memory Management for Multicores Having Global Address Space
inferred← citeshttps://doi.org/10.1007/978-3-540-69330-7_25openalex-snapshot
Compiler Control Power Saving Scheme for Multi Core Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-77704-5_45openalex-snapshot
Performance Evaluation of Compiler Controlled Power Saving Scheme
inferred← citeshttps://doi.org/10.1007/978-3-642-19595-2_13openalex-snapshot
Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores
inferred← citeshttps://doi.org/10.1007/978-3-642-24568-8_11openalex-snapshot
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture
inferred← citeshttps://doi.org/10.1007/bfb0017245openalex-snapshot
Data localization using loop aligned decomposition for macro-dataflow processing
inferred← citeshttps://doi.org/10.1007/bfb0025878openalex-snapshot
The data partitioning graph: Extending data and control dependencies for data partitioning
inferred← citeshttps://doi.org/10.1016/j.parco.2014.11.004openalex-snapshot
Parallelizing with BDSC, a resource-constrained scheduling algorithm for shared and distributed memory systems
inferred← citeshttps://doi.org/10.1016/s0065-2458(08)60287-9openalex-snapshot
Managing Control Asynchrony on SIMD Machines—a Survey
inferred← citeshttps://doi.org/10.1016/s0167-8191(98)00026-xopenalex-snapshot
A data-localization compilation scheme using partial-static task assignment for Fortran coarse-grain parallel processing
inferred← citeshttps://doi.org/10.1023/a:1023038702472openalex-snapshot
Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP
inferred← citeshttps://doi.org/10.1109/5.214548openalex-snapshot
Automatic program parallelization
inferred← citeshttps://doi.org/10.1109/aspdac.2008.4484049openalex-snapshot
Software-cooperative power-efficient heterogeneous multi-core for media processing
inferred← citeshttps://doi.org/10.1109/cgames.2012.6314554openalex-snapshot
Enhancing the performance of a multiplayer game by using a parallelizing compiler
inferred← citeshttps://doi.org/10.1109/coolchips.2013.6547921openalex-snapshot
Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler
inferred← citeshttps://doi.org/10.1109/icpp.2009.6openalex-snapshot
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme
inferred← citeshttps://doi.org/10.1109/iwia.1999.898840openalex-snapshot
Near fine grain parallel processing using static scheduling on single chip multiprocessors
inferred← citeshttps://doi.org/10.1109/iwia.2002.1035019openalex-snapshot
Multigrain parallel processing for JPEG encoding on a single chip multiprocessor
inferred← citeshttps://doi.org/10.1109/jssc.2008.917531openalex-snapshot
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding
inferred← citeshttps://doi.org/10.1109/pacrim.1995.519406openalex-snapshot
Hierarchical macro-dataflow computation scheme
inferred← citeshttps://doi.org/10.1109/pacrim.1995.519427openalex-snapshot
A data-localization scheme using task-fusion for macro-dataflow computation
inferred← citeshttps://doi.org/10.1109/pacrim.1995.519536openalex-snapshot
Compilation scheme for near fine grain parallel processing on a multiprocessor system without explicit synchronization
inferred← citeshttps://doi.org/10.1109/pcee.2002.1115213openalex-snapshot
Multigrain automatic parallelization in Japanese Millennium Project IT21. Advanced Parallelizing Compiler
inferred← citeshttps://doi.org/10.1109/vlsic.2008.4585931openalex-snapshot
Power-efficient heteregoneous parallelism for digital convergence
inferred← citeshttps://doi.org/10.1145/1119772.1119898openalex-snapshot
MAPLE chip
inferred← citeshttps://doi.org/10.1145/237578.237586openalex-snapshot
Data-localization for Fortran macro-dataflow computation using partial static task assignment
inferred← citeshttps://doi.org/10.1145/3002125.3002129openalex-snapshot
Reducing parallelizing compilation time by removing redundant analysis
inferred← citeshttps://doi.org/10.1145/305138.305207openalex-snapshot
SMARTS
inferred← citeshttps://doi.org/10.1541/ieejeiss1987.113.11_919openalex-snapshot
III. Software for Parallel Processing
inferred← citeshttps://doi.org/10.1587/transinf.e96.d.1645openalex-snapshot
A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards
inferred← citeshttps://doi.org/10.2197/ipsjdc.2.280openalex-snapshot
Limits of Thread-Level Parallelism in Non-numerical Programs
inferred← citeshttps://doi.org/10.24297/ijct.v23i.9472openalex-snapshot
LLVM-IR Instruction Latency Estimation Using Deep Neural Networks for a Software–Hardware Interface for Multi-Many-Cores
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.