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Efficient modeling of memory arrays in symbolic ternary simulation

https://doi.org/10.1007/bfb0054169
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-63166-6_25openalex-snapshot
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
inferredcites →https://doi.org/10.1007/3-540-63166-6_38openalex-snapshot
Efficient modeling of memory arrays in symbolic simulation
inferredcites →https://doi.org/10.1007/bf01383966openalex-snapshot
Formal verification by symbolic evaluation of partially-ordered trajectories
inferredcites →https://doi.org/10.1109/43.771176openalex-snapshot
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
inferredcites →https://doi.org/10.1145/123186.123223openalex-snapshot
Sequential circuit verification using symbolic model checking
inferredcites →https://doi.org/10.1145/127601.127701openalex-snapshot
Formal hardware verification by symbolic ternary trajectory evaluation
inferredcites →https://doi.org/10.1145/127601.127702openalex-snapshot
Representing circuits more efficiently in symbolic model checking
inferredcites →https://doi.org/10.1145/136035.136043openalex-snapshot
Symbolic Boolean manipulation with ordered binary-decision diagrams

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44798-9_30openalex-snapshot
Using Abstract Specifications to Verify PowerPC™ Custom Memories by Symbolic Trajectory Evaluation
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_3openalex-snapshot
Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking
inferred← citeshttps://doi.org/10.1007/978-3-319-10575-8_25openalex-snapshot
Symbolic Trajectory Evaluation
inferred← citeshttps://doi.org/10.1007/s10703-005-2250-1openalex-snapshot
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor
inferred← citeshttps://doi.org/10.1016/b978-0-12-800727-3.00010-1openalex-snapshot
Dealing with complexity
inferred← citeshttps://doi.org/10.1016/b978-0-323-95612-3.00010-0openalex-snapshot
Dealing with complexity
inferred← citeshttps://doi.org/10.1109/csd.1998.657552openalex-snapshot
Verification of pipelined microprocessors by correspondence checking in symbolic ternary simulation
inferred← citeshttps://doi.org/10.1109/dac.1999.781348openalex-snapshot
Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
inferred← citeshttps://doi.org/10.1109/dac.2002.1012603openalex-snapshot
Handling special constructs in symbolic simulation
inferred← citeshttps://doi.org/10.1109/date.2004.1268859openalex-snapshot
Exploiting signal unobservability for efficient translation to CNF in formal verification of microprocessors
inferred← citeshttps://doi.org/10.1109/hldvt.2001.972820openalex-snapshot
A language formalism for verification of PowerPC/sup TM/ custom memories using compositions of abstract specifications
inferred← citeshttps://doi.org/10.1109/iccd.1998.727081openalex-snapshot
Incorporating timing constraints in the efficient memory model for symbolic ternary simulation
inferred← citeshttps://doi.org/10.1109/tcad.2005.850814openalex-snapshot
An industrially effective environment for formal hardware verification
inferred← citeshttps://doi.org/10.1109/tcad.2005.852051openalex-snapshot
Schematic array models for associative and non-associative memory circuits
inferred← citeshttps://doi.org/10.1145/309847.309967openalex-snapshot
Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
inferred← citeshttps://doi.org/10.1145/513918.513947openalex-snapshot
Handling special constructs in symbolic simulation
inferred← citeshttps://doi.org/10.1504/ijes.2005.008815openalex-snapshot
TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories
inferred← citeshttps://doi.org/10.5555/1998496.1998512openalex-snapshot
Coping with Moore's law (and more): supporting arrays in state-of-the-art model checkers
inferred← citeshttps://doi.org/10.5555/968878.969057openalex-snapshot
Extraction of schematic array models for memory circuits
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