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Model checking via reachability testing for timed automata
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/inco.1994.1028openalex-snapshot
Characteristic Formulas for Processes with Divergence
inferredcites →https://doi.org/10.1006/inco.1994.1045openalex-snapshot
Symbolic Model Checking for Real-Time Systems
inferredcites →https://doi.org/10.1006/inco.1994.1092openalex-snapshot
Reasoning about Infinite Computations
inferredcites →https://doi.org/10.1007/3-540-54233-7_129openalex-snapshot
Computing behavioural relations, logically
inferredcites →https://doi.org/10.1007/3-540-56496-9_24openalex-snapshot
Decidability of bisimulation equivalences for parallel timer processes
inferredcites →https://doi.org/10.1007/3-540-60045-0_64openalex-snapshot
Automated analysis of an audio control protocol
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An automata-theoretic approach to linear temporal logic
inferredcites →https://doi.org/10.1007/3-540-61474-5_73openalex-snapshot
Verification of an Audio Protocol with bus collision using Uppaal
inferredcites →https://doi.org/10.1007/3-540-63166-6_20openalex-snapshot
STARI: A case study in compositional and hierarchical timing verification
inferredcites →https://doi.org/10.1007/bfb0020949openalex-snapshot
UPPAAL — a tool suite for automatic verification of real-time systems
inferredcites →https://doi.org/10.1007/bfb0028550openalex-snapshot
Searching Constant Width Mazes Captures the AC0 Hierarchy
inferredcites →https://doi.org/10.1007/bfb0039080openalex-snapshot
Real-time behaviour of asynchronous agents
inferredcites →https://doi.org/10.1016/0304-3975(84)90113-0openalex-snapshot
Testing equivalences for processes
inferredcites →https://doi.org/10.1016/0304-3975(94)90010-8openalex-snapshot
A theory of timed automata
inferredcites →https://doi.org/10.1016/0890-5401(91)90030-6openalex-snapshot
Bisimulation through probabilistic testing
inferredcites →https://doi.org/10.1017/s0960129500000189openalex-snapshot
Quantales, observational logic and process semantics
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/lics.1990.113766openalex-snapshot
Model-checking for real-time systems
inferredcites →https://doi.org/10.1145/225058.225162openalex-snapshot
What's decidable about hybrid automata?
inferredcites →https://doi.org/10.1145/2455.2460openalex-snapshot
Algebraic laws for nondeterminism and concurrency
inferredcites →https://doi.org/10.2307/2586693openalex-snapshot
Topological completeness for higher-order logic
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From Timed Automata to Logic - and Back
inferredcites →https://doi.org/10.7146/brics.v3i24.20005openalex-snapshot
Modelling and Analysis of a Collision Avoidance Protocol using SPIN and UPPAAL
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Classifying Toposes for First Order Theories
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On the Arithmetical Content of Restricted Forms of Comprehension, Choice and General Uniform Boundedness
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Relational Reasoning about Contexts
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A Characterization of Finitary Bisimulation
inferredcites →https://doi.org/10.7146/brics.v4i27.18953openalex-snapshot
Zero-Knowledge Proofs for Finite Field Arithmetic or: Can Zero-Knowledge be for Free?
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Span Programs and General Secure Multi-Party Computation
inferredcites →https://doi.org/10.7146/brics.v4i29.18955openalex-snapshot
Model Checking via Reachability Testing for Timed Automata
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9780470611012.ch4openalex-snapshot
Model Checking Timed Automata
inferred← citeshttps://doi.org/10.1002/cpe.6974openalex-snapshot
Execution trace‐based model verification to analyze multicore and real‐time systems
inferred← citeshttps://doi.org/10.1007/3-540-45449-7_8openalex-snapshot
Verification of Embedded Software: Problems and Perspectives
inferred← citeshttps://doi.org/10.1007/3-540-45739-9_1openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-45739-9_25openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-48119-2_18openalex-snapshot
Formula Based Abstractions of Transition Systems for Real-Time Model Checking
inferred← citeshttps://doi.org/10.1007/3-540-48340-3_12openalex-snapshot
Is Your Model Checker on Time?
inferred← citeshttps://doi.org/10.1007/3-540-48778-6_17openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/3-540-49019-1_4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-40914-2_8openalex-snapshot
Compositional Liveness-Preserving Conformance Testing of Timed I/O Automata
inferred← citeshttps://doi.org/10.1007/978-3-031-85134-6_5openalex-snapshot
Parallel Composition of Constraint Automata
inferred← citeshttps://doi.org/10.1007/978-3-319-28678-5_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-53946-1_8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-94496-8_3openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-27755-2_3openalex-snapshot
Timed Automata: Semantics, Algorithms and Tools
inferred← citeshttps://doi.org/10.1007/978-3-540-27863-4_28openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-39893-6_29openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-39893-6_30openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-45069-6_37openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-49382-2_22openalex-snapshot
The Power of Reachability Testing for Timed Automata
inferred← citeshttps://doi.org/10.1007/978-3-540-75698-9_6openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-85780-8_17openalex-snapshot
When Is Reachability Intrinsically Decidable?
inferred← citeshttps://doi.org/10.1007/978-3-642-04368-0_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-11486-1_3openalex-snapshot
Compositional and Quantitative Model Checking (Extended Abstract)
inferred← citeshttps://doi.org/10.1007/s00236-003-0135-6openalex-snapshot
Timed automata with urgent transitions
inferred← citeshttps://doi.org/10.1007/s10009-006-0011-0openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10009-014-0312-7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s100090100048openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10270-017-0588-7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10703-006-0012-3openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10703-010-0103-zopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10703-011-0140-2openalex-snapshot
Interrupt Timed Automata: verification and expressiveness
inferred← citeshttps://doi.org/10.1007/s10766-020-00689-5openalex-snapshot
Automated Generation of Model-Based Constraints for Common Multi-core and Real-Time Applications Using Execution Tracing
inferred← citeshttps://doi.org/10.1007/s10849-010-9127-4openalex-snapshot
Timed Modal Logics for Real-Time Systems
inferred← citeshttps://doi.org/10.1007/s11241-011-9122-0openalex-snapshot
Efficient verification of distributed real-time systems with broadcasting behaviors
inferred← citeshttps://doi.org/10.1007/s11241-014-9208-6openalex-snapshot
Parameter synthesis for hierarchical concurrent real-time systems
inferred← citeshttps://doi.org/10.1016/s0304-3975(02)00334-1openalex-snapshot
The power of reachability testing for timed automata
inferred← citeshttps://doi.org/10.1016/s1567-8326(02)00022-xopenalex-snapshot
Is your model checker on time? On the complexity of model checking for timed modal logics
inferred← citeshttps://doi.org/10.1017/cbo9780511778421.008openalex-snapshot
Three lectures on automatic structures
inferred← citeshttps://doi.org/10.1023/a:1018938205540openalex-snapshot
Specification and analysis of real-time systems with PARAGON
inferred← citeshttps://doi.org/10.1023/a:1025132427497openalex-snapshot
Compact Data Structures and State-Space Reduction for Model-Checking Real-Time Systems
inferred← citeshttps://doi.org/10.1023/a:1026534200187openalex-snapshot
Logic Based Abstractions of Real-Time Systems
inferred← citeshttps://doi.org/10.1049/ic:19980529openalex-snapshot
Modelling and analysis of broadcasting embedded control systems
inferred← citeshttps://doi.org/10.1109/hase.1999.809471openalex-snapshot
Using Modechart modules for testing formal specifications
inferred← citeshttps://doi.org/10.1109/icawst.2013.6765522openalex-snapshot
Modeling real-time system performance with respect to scheduling analysis
inferred← citeshttps://doi.org/10.1109/iceccs.2012.29openalex-snapshot
Parameter synthesis for hierarchical concurrent real-time systems
inferred← citeshttps://doi.org/10.1109/iceccs.2013.13openalex-snapshot
Modeling and Verifying Real-Time Properties of Reactive Systems
inferred← citeshttps://doi.org/10.1109/iceccs.2013.26openalex-snapshot
Observer Patterns for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/iciw.2007.14openalex-snapshot
An Adaptable Formal Model for Web Services Protocols
inferred← citeshttps://doi.org/10.1109/icniconsmcl.2006.150openalex-snapshot
Modeling and Verification of a Time-triggered Networking Protocol
inferred← citeshttps://doi.org/10.1109/isorc.2016.18openalex-snapshot
Generation of SystemVerilog Observers from SysML and MARTE/CCSL
inferred← citeshttps://doi.org/10.1109/rsp.2012.6380695openalex-snapshot
Automatic generation of observers from MARTE/CCSL
inferred← citeshttps://doi.org/10.1109/rtcsa.2014.6910519openalex-snapshot
Impact analysis for timing requirements on real-time systems
inferred← citeshttps://doi.org/10.1109/sies.2010.5551372openalex-snapshot
VHDL observers for clock constraint checking
inferred← citeshttps://doi.org/10.1109/tac.2016.2606082openalex-snapshot
Minimum Resource Commitment for Reachability Specifications in a Discrete Time Linear Setting
inferred← citeshttps://doi.org/10.1145/1266894.1266903openalex-snapshot
Seamless formal verification of complex event processing applications
inferred← citeshttps://doi.org/10.1145/3622786openalex-snapshot
Extensible Proof Systems for Infinite-State Systems
inferred← citeshttps://doi.org/10.1155/2016/9792462openalex-snapshot
Detection of Common Problems in Real-Time and Multicore Systems Using Model-Based Constraints
inferred← citeshttps://doi.org/10.1177/00375497251340070openalex-snapshot
Verification of quantitative temporal properties in RealTime-DEVS
inferred← citeshttps://doi.org/10.12988/ams.2016.65208openalex-snapshot
Modeling of railway networks using timed automata
inferred← citeshttps://doi.org/10.1504/ijccbs.2014.059593openalex-snapshot
A formal framework to specify and verify real-time properties on critical systems
inferred← citeshttps://doi.org/10.22215/etd/2013-09622openalex-snapshot
Verification methodology for DEVS models
inferred← citeshttps://doi.org/10.3166/isi.12.5.133-157openalex-snapshot
Mise en œuvre de composants MDA pour la validation formelle de modèles de systèmes d'information embarqués
inferred← citeshttps://doi.org/10.3176/phys.math.1998.3.06openalex-snapshot
CONTEXT-DEPENDENTMINIMIZATION OF STATE/EVENT SYSTEMS
inferred← citeshttps://doi.org/10.5555/1639809.1655372openalex-snapshot
Verification of real-time DEVS models
inferred← citeshttps://doi.org/10.5555/1775223.1775229openalex-snapshot
Adapting the UPPAAL model of a distributed lift system
inferred← citeshttps://doi.org/10.70675/2c74c3e6zd08ez48f3z8ca3z817c32cab8beopenalex-snapshot
Parallelism and modular proof in differential dynamic logic
inferred← citeshttps://doi.org/10.70675/9909c56dz2678z4612zba67z9d3f86555c83openalex-snapshot
Synthesis of correct-by-design schedulers for hybrid systems
inferred← citeshttps://doi.org/10.70675/f26a3dcfz905dz4f2ezaa66z0d530549012fopenalex-snapshot
Synchronizing automata and coding theory
inferred← citeshttps://doi.org/10.7146/brics.v4i29.18955openalex-snapshot
Model Checking via Reachability Testing for Timed Automata
inferred← citeshttps://doi.org/10.7146/brics.v4i30.18956openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v4i31.18957openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v4i32.18958openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v4i33.18959openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v4i34.18960openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v4i35.18961openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v4i36.18962openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v4i38.18964openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v6i32.20101openalex-snapshot
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inferred← citeshttps://doi.org/10.7146/brics.v6i8.20065openalex-snapshot
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