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Static partial order reduction
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Formal verification of a partial-order reduction technique for model checking
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Partial order reduction: Model-checking using representatives
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Partial-order reduction in symbolic state space exploration
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An Improvement in Formal Verification
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Combining partial order reductions with on-the-fly model-checking
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A stubborn attack on state explosion
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Computer-aided verification of coordinating processes: The automata-theoretic approach
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A stubborn attack on state explosion
inferredcites →https://doi.org/10.1109/43.662676openalex-snapshot
Formal verification of digital systems by automatic reduction of data paths
inferredcites →https://doi.org/10.1109/istcs.1995.377038openalex-snapshot
A partial order approach to branching time logic model checking
inferredcites →https://doi.org/10.1109/pccc.1992.200529openalex-snapshot
A fast protocol conversion technique using reduction of state transition graphs
inferredcites →https://doi.org/10.1142/9789812389701_0011openalex-snapshot
FORMAL DESCRIPTION TECHNIQUES
inferredcites →https://doi.org/10.1145/226295.226324openalex-snapshot
Using partial-order methods in the formal validation of industrial concurrent programs
inferredcites →https://doi.org/10.1515/9781400864041openalex-snapshot
Computer-Aided Verification of Coordinating Processes
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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