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An algorithm for the partitioning of logic circuits

https://doi.org/10.1049/ip-e.1984.0021
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1145/800139.804515openalex-snapshot
Test generation costs analysis and projections

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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PEST: A Tool for Implementing Pseudo-Exhaustive Self-Test
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Automatisierung des Entwurfs vollständig testbarer Schaltungen
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Fault Models
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A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
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Cooperative multi-thread parallel tabu search with an application to circuit partitioning
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Graph partitioning applied to the logic testing of combinational circuits
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Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
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Deductive fault diagnosis in digital circuits: a survey
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A method for pseudo-exhaustive test pattern generation
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A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits
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A timing-driven pseudoexhaustive testing for VLSI circuits
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Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets
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Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits
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Low Power Pseudoexhaustive Testing with Cellular Automata
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Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing
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Circuit partitioning for pseudo-exhaustive test
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PEST-a tool for implementing pseudo-exhaustive self test
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Efficient Segmentation For Pseudo-exhaustive BIST
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Tools and devices supporting the pseudo-exhaustive test
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PEST-a tool for implementing pseudo-exhaustive self test
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Pseudo-exhaustive test and segmentation: formal definitions and extended fault coverage results
inferred← citeshttps://doi.org/10.1109/iccad.1993.580154openalex-snapshot
Logic partitioning to pseudo-exhaustive test for BIST design
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On partitioning for pseudo exhaustive testing of VLSI circuits
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A timing-driven pseudo-exhaustive testing of VLSI circuits
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An efficient algorithm to partition the combinational circuits for pseudoexhaustive testing
inferred← citeshttps://doi.org/10.1109/secon.1991.147928openalex-snapshot
On controllability estimation to aid in partitioning logic circuits
inferred← citeshttps://doi.org/10.1109/test.1988.207832openalex-snapshot
Reconfigurable hardware for pseudoexhaustive test
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Generating pseudo-exhaustive vectors for external testing
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Practical partitioning for testability with time-shared boundary scan
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A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
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A design for testability technique for test pattern generation with LFSRs
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An efficient partitioning strategy for pseudo-exhaustive testing
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A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing
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Fault behavior dictionary for simulation of device-level transients
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Logic partitioning to pseudo-exhaustive test for BIST design
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Tools and devices supporting the pseudo-exhaustive test
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PEST-a tool for implementing pseudo-exhaustive self test
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