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Four-slot fully asynchronous communication mechanism
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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inferredcites →https://doi.org/10.1016/0304-3975(83)90114-7openalex-snapshot
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inferredcites →https://doi.org/10.1049/piee.1976.0212openalex-snapshot
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inferredcites →https://doi.org/10.1109/tc.1981.6312173openalex-snapshot
General theory of metastable operation
inferredcites →https://doi.org/10.1145/357195.357199openalex-snapshot
A New Solution to Lamport's Concurrent Programming Problem Using Small Shared Variables
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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inferred← citeshttps://doi.org/10.1007/3-540-47884-1_17openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-1-84882-258-0_19openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-1-84882-736-3_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-031-40436-8_5openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-92432-8_4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s00165-014-0310-2openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/s1474-6670(17)45965-9openalex-snapshot
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inferred← citeshttps://doi.org/10.1049/ic:20030032openalex-snapshot
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inferred← citeshttps://doi.org/10.1049/ip-e.1992.0006openalex-snapshot
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inferred← citeshttps://doi.org/10.1049/sej.1995.0014openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/async.2000.836997openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/async.2001.914076openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/async.2005.27openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/cluster.2017.84openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/csd.2001.981765openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ecbs.1994.331683openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ecbs.1997.581893openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/emwrt.1992.637486openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/emwrts.1998.684918openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icdcsw.2003.1203552openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mm.2002.1134344openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/real.1993.393507openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/real.1998.739772openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00013openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/rtas54340.2022.00014openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/rtcsa.1999.811236openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/rtcsa.1999.811240openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/rtss.2015.32openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2006.42openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1978802.1978814openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2512989.2512994openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3376897.3377861openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3477013openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3477314.3507231openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/381766.381770openalex-snapshot
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inferred← citeshttps://doi.org/10.14236/ewic/fa1996.3openalex-snapshot
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inferred← citeshttps://doi.org/10.21236/ada412984openalex-snapshot
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inferred← citeshttps://doi.org/10.21236/ada431078openalex-snapshot
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inferred← citeshttps://doi.org/10.25405/ncl.34128837openalex-snapshot
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inferred← citeshttps://doi.org/10.25405/ncl.34128840openalex-snapshot
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inferred← citeshttps://doi.org/10.25405/ncl.34128930openalex-snapshot
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inferred← citeshttps://doi.org/10.25405/ncl.34129035openalex-snapshot
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inferred← citeshttps://doi.org/10.25405/ncl.34129233openalex-snapshot
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inferred← citeshttps://doi.org/10.29007/l2spopenalex-snapshot
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inferred← citeshttps://doi.org/10.48456/tr-726openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.1304.2936openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.1601.02132openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.1803.10067openalex-snapshot
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inferred← citeshttps://doi.org/10.5070/sr32158647openalex-snapshot
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