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SPEC CPU2000: measuring CPU performance in the New Millennium
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S/DC: A storage and energy efficient data prefetcher
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Salvaging chips with caches beyond repair
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An out-of-order superscalar processor on FPGA: The ReOrder Buffer design
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What to adapt in a high-performance microprocessor
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What to adapt in a high-performance microprocessor
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Instruction Precomputation for Fault Detection
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Re-NUCA: Boosting CMP Performance Through Block Replication
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Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
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System Call Redirection: A Practical Approach to Meeting Real-World Virtual Machine Introspection Needs
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Fine-Grained Characterization of Faults Causing Long Latency Crashes in Programs
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Modeling Soft-Error Propagation in Programs
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Modeling Input-Dependent Error Propagation in Programs
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Investigating Average versus Worst-Case Timing Behavior of Data Caches and Data Scratchpads
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Memory Bandwidth Aware Scheduling for SMP Cluster Nodes
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DIME: Time-aware dynamic binary instrumentation using rate-based resource allocation
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Thermal characterization of TSV based 3D stacked ICs
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Static prediction of recursion frequency using machine learning to enable hot spot optimizations
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Enforcing Quality of Service Through Hardware Resource Aware Process Scheduling
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Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model
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Reconfigurable Functional Units for Scientific Superscalar Processors
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Evaluating Compiler IR-Level Selective Instruction Duplication with Realistic Hardware Errors
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CARS: a new code generation framework for clustered ILP processors
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A new memory monitoring scheme for memory-aware scheduling and partitioning
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Memory latency-tolerance approaches for Itanium processors: out-of-order execution vs. speculative precomputation
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Caches and hash trees for efficient memory integrity verification
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Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
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