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Dynamic current mode logic (DyCML): a new low-power high-performance logic style

https://doi.org/10.1109/4.910495
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-2325-3openalex-snapshot
Low Power Digital CMOS Design
inferredcites →https://doi.org/10.1109/4.509871openalex-snapshot
Performance of CMOS differential circuits
inferredcites →https://doi.org/10.1109/4.597298openalex-snapshot
Low-power logic styles: CMOS versus pass-transistor logic
inferredcites →https://doi.org/10.1109/cicc.2000.852699openalex-snapshot
Dynamic current mode logic (DyCML), a new low-power high-performance logic family
inferredcites →https://doi.org/10.1109/jssc.1982.1051786openalex-snapshot
High-speed compact circuits with CMOS
inferredcites →https://doi.org/10.1201/9781315275567openalex-snapshot
Computer Arithmetic Algorithms

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Three Phase Dynamic Current Mode Logic: A More Secure DyCML to Achieve a More Balanced Power Consumption
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CML Gates with Modified Current Source
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A New Improved MCML Logic for DPA Resistant Circuits
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Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices
inferred← citeshttps://doi.org/10.7567/jjap.54.04de01openalex-snapshot
Nonvolatile field-programmable gate array using 2-transistor–1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic
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