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Efficient BIST TPG design and test set compaction via input reduction

https://doi.org/10.1109/43.712101
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Built-in test for VLSI: Pseudorandom techniques
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Digital Systems : Testing and Testable Design
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The use of linear sums in exhaustive testing
inferredcites →https://doi.org/10.1109/43.137523openalex-snapshot
The testability-preserving concurrent decomposition and factorization of Boolean expressions
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COMPACTEST: a method to generate compact test sets for combinational circuits
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3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits
inferredcites →https://doi.org/10.1109/43.275361openalex-snapshot
On necessary and nonconflicting assignments in algorithmic test pattern generation
inferredcites →https://doi.org/10.1109/43.3140openalex-snapshot
SOCRATES: a highly efficient automatic test pattern generation system
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Improved deterministic test pattern generation with applications to redundancy identification
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Circuits for pseudoexhaustive test pattern generation
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Digital Systems Testing and Testable Design
inferredcites →https://doi.org/10.1109/iccad.1992.279408openalex-snapshot
Configuring multiple scan chains for minimum test time
inferredcites →https://doi.org/10.1109/iccad.1993.580117openalex-snapshot
An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers
inferredcites →https://doi.org/10.1109/icvd.1994.282710openalex-snapshot
Low-cost redundancy identification for combinational circuits
inferredcites →https://doi.org/10.1109/iscas.1989.100747openalex-snapshot
Combinational profiles of sequential benchmark circuits
inferredcites →https://doi.org/10.1109/jssc.1980.1051391openalex-snapshot
Built-in test for complex digital integrated circuits
inferredcites →https://doi.org/10.1109/tc.1984.1676477openalex-snapshot
Verification Testing—A Pseudoexhaustive Test Technique
inferredcites →https://doi.org/10.1109/tct.1959.1086506openalex-snapshot
The Theory of Autonomous Linear Sequential Networks
inferredcites →https://doi.org/10.1109/test.1992.527904openalex-snapshot
One-pass redundancy identification and removal
inferredcites →https://doi.org/10.1109/test.1992.527905openalex-snapshot
Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci
inferredcites →https://doi.org/10.1137/0213005openalex-snapshot
Clique Covering of Graphs IV. Algorithms
inferredcites →https://doi.org/10.5555/191326.191377openalex-snapshot
Random pattern testable logic synthesis

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A Multiple Compatible Compression Scheme Based on Tri-state Signal
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Test Pattern Generator Design Optimization Based on Genetic Algorithm
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Deterministic Test Pattern Generator Design
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Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees
inferred← citeshttps://doi.org/10.1007/s10836-013-5380-1openalex-snapshot
A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic
inferred← citeshttps://doi.org/10.1007/s11227-019-03071-6openalex-snapshot
A variable-length compatible compression scheme based on tristate signals
inferred← citeshttps://doi.org/10.1016/b978-012370597-6/50009-3openalex-snapshot
Logic Built-In Self-Test
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A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
inferred← citeshttps://doi.org/10.1023/a:1014993509806openalex-snapshot
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
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Arithmetic module-based built-in self test architecture for two-pattern testing
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Reconfigurable broadcast scan compression using relaxation-based test vector decomposition
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IOC-LP: hybrid test data compression∕decompression scheme for low power testing
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System-on-a-chip test-data compression and decompression architectures based on Golomb codes
inferred← citeshttps://doi.org/10.1109/apasic.1999.824092openalex-snapshot
Input grouping method considering nodal connectivity for BIST test time reduction
inferred← citeshttps://doi.org/10.1109/apccas.2004.1412721openalex-snapshot
Efficient testing and design-for-testability schemes for multimedia cores: a case study on DCT circuits
inferred← citeshttps://doi.org/10.1109/aspdac.2008.4484031openalex-snapshot
A new low energy BIST using a statistical code
inferred← citeshttps://doi.org/10.1109/ats.2002.1181734openalex-snapshot
Reducing test application time and power dissipation for scan-based testing via multiple clock disabling
inferred← citeshttps://doi.org/10.1109/ats.2003.1250772openalex-snapshot
Reducing scan shifts using folding scan trees
inferred← citeshttps://doi.org/10.1109/ats.2003.1250774openalex-snapshot
Improving test quality of scan-based BIST by scan chain partitioning
inferred← citeshttps://doi.org/10.1109/ats.2003.1250798openalex-snapshot
Optimal scan tree construction with test vector modification for test compression
inferred← citeshttps://doi.org/10.1109/ats.2003.1250848openalex-snapshot
Sharing BIST with multiple cores for system-on-a-chip
inferred← citeshttps://doi.org/10.1109/ats.2004.61openalex-snapshot
Multiple Scan Tree Design with Test Vector Modification
inferred← citeshttps://doi.org/10.1109/ats.2004.78openalex-snapshot
Scan-Based BIST Using an Improved Scan Forest Architecture
inferred← citeshttps://doi.org/10.1109/ats.2005.112openalex-snapshot
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST
inferred← citeshttps://doi.org/10.1109/ats.2007.41openalex-snapshot
A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos
inferred← citeshttps://doi.org/10.1109/delta.2004.10014openalex-snapshot
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure
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A multi-output technique for high fault coverage in test-per-scan BIST
inferred← citeshttps://doi.org/10.1109/ets.2014.6847846openalex-snapshot
Concurrent online BIST for sequential circuits exploiting input reduction and output space compaction
inferred← citeshttps://doi.org/10.1109/iccad.2004.1382670openalex-snapshot
Frugal linear network-based test decompression for drastic test cost reductions
inferred← citeshttps://doi.org/10.1109/iccd.1998.727020openalex-snapshot
Efficient BIST TPG design and test set compaction for delay testing via input reduction
inferred← citeshttps://doi.org/10.1109/icces48766.2020.9138068openalex-snapshot
Implementation of Hybrid LBIST Mechanism in Digital Circuits for Test Pattern Generation and Test Time Reduction
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Improving generation method for test pattern based on BDD learning
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Channel width test data compression under a limited number of test inputs and outputs
inferred← citeshttps://doi.org/10.1109/iolts.2008.37openalex-snapshot
Deterministic Built-in TPG with Segmented FSMs
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Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip
inferred← citeshttps://doi.org/10.1109/tcad.2002.1013898openalex-snapshot
A new built-in TPG method for circuits with random pattern resistant faults
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SPIRIT: a highly robust combinational test generation algorithm
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Test pattern generation and clock disabling for simultaneous test time and power reduction
inferred← citeshttps://doi.org/10.1109/tcad.2005.847943openalex-snapshot
Improving test effectiveness of scan-based BIST by scan chain partitioning
inferred← citeshttps://doi.org/10.1109/tcsii.2007.892393openalex-snapshot
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture
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Design and test of a highthroughput cabac encoder
inferred← citeshttps://doi.org/10.1109/test.2000.894274openalex-snapshot
A mixed mode BIST scheme based on reseeding of folding counters
inferred← citeshttps://doi.org/10.1109/test.2001.966712openalex-snapshot
Two-dimensional test data compression for scan-based deterministic BIST
inferred← citeshttps://doi.org/10.1109/test.2004.1387357openalex-snapshot
Data compression for multiple scan chains using dictionaries with corrections
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Complex Field Fault Modeling-Based Optimal Frequency Selection in Linear Analog Circuit Fault Diagnosis
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MICRO: a new hybrid test data compression/decompression scheme
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Test pattern generation and clock disabling for test time and power reduction
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Test data compression for system-on-a-chip using Golomb codes
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Reducing test application time for built-in-self-test test pattern generators
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An Efficient Two-Dimension BIST Compression Approach
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A new low energy BIST using a statistical code
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