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OS-Based NUMA Optimization: Tackling the Case of Truly Multi-thread Applications with Non-partitioned Virtual Page Accesses

https://doi.org/10.1109/ccgrid.2016.91

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-41527-2_9openalex-snapshot

Exploiting Locality in Lease-Based Replicated Transactional Memory via Task Migration

inferredcites →https://doi.org/10.1007/s10586-013-0307-2openalex-snapshot

PEBIL: binary instrumentation for practical data-intensive program analysis

inferredcites →https://doi.org/10.1016/j.jpdc.2008.05.006openalex-snapshot

Hardware monitors for dynamic page migration

inferredcites →https://doi.org/10.1016/j.jpdc.2010.08.017openalex-snapshot

On cluster resource allocation for multiple parallel task graphs

inferredcites →https://doi.org/10.1109/ccgrid.2011.83openalex-snapshot

EZTrace: A Generic Framework for Performance Analysis

inferredcites →https://doi.org/10.1109/cluster.2012.47openalex-snapshot

Optimizing Process-to-Core Mappings for Application Level Multi-dimensional MPI Communications

inferredcites →https://doi.org/10.1109/hpcc.2010.114openalex-snapshot

Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors

inferredcites →https://doi.org/10.1109/iiswc.2005.1526000openalex-snapshot

Reducing overheads for acquiring dynamic memory traces

inferredcites →https://doi.org/10.1109/iiswc.2009.5306792openalex-snapshot

A communication characterisation of Splash-2 and Parsec

inferredcites →https://doi.org/10.1109/ipdps.2012.55openalex-snapshot

Optimization of Parallel Discrete Event Simulator for Multi-core Systems

inferredcites →https://doi.org/10.1109/pads.1995.404306openalex-snapshot

Buffer management in shared-memory time warp systems

inferredcites →https://doi.org/10.1109/sbac-pad.2014.22openalex-snapshot

Optimizing Memory Locality Using a Locality-Aware Page Table

inferredcites →https://doi.org/10.1109/tpds.2013.193openalex-snapshot

Parallel Discrete Event Simulation for Multi-Core Systems: Analysis and Optimization

inferredcites →https://doi.org/10.1109/tpds.2014.2323967openalex-snapshot

Autonomic State Management for Optimistic Simulation Platforms

inferredcites →https://doi.org/10.1145/1122971.1122987openalex-snapshot

Hardware profile-guided automatic page placement for ccNUMA systems

inferredcites →https://doi.org/10.1145/1127577.1127585openalex-snapshot

ALITER

inferredcites →https://doi.org/10.1145/1183401.1183451openalex-snapshot

MPIPP

inferredcites →https://doi.org/10.1145/1854273.1854314openalex-snapshot

Handling the problems and opportunities posed by multiple on-chip memory controllers

inferredcites →https://doi.org/10.1145/214282.214330openalex-snapshot

Buffer management in shared-memory Time Warp systems

inferredcites →https://doi.org/10.1145/2425248.2425250openalex-snapshot

Load sharing for optimistic parallel simulations on multi core machines

inferredcites →https://doi.org/10.1145/2451116.2451157openalex-snapshot

Traffic management

inferredcites →https://doi.org/10.1145/249204.249207openalex-snapshot

Adaptive memory management and optimism control in time warp

inferredcites →https://doi.org/10.1145/2628071.2628077openalex-snapshot

Compiler support for selective page migration in NUMA architectures

inferredcites →https://doi.org/10.1145/2628071.2628085openalex-snapshot

kMAF

inferredcites →https://doi.org/10.1145/2769458.2769479openalex-snapshot

NUMA Time Warp

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/spe.2731openalex-snapshot

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

inferred← citeshttps://doi.org/10.1002/spe.3236openalex-snapshot

Strategies and software support for the management of hardware performance counters

inferred← citeshttps://doi.org/10.1007/978-3-031-39847-6_15openalex-snapshot

NoGar: A Non-cooperative Game for Thread Pinning in Array Databases

inferred← citeshttps://doi.org/10.1007/978-3-319-91074-1_4openalex-snapshot

State-of-the-Art Sharing-Aware Mapping Methods

inferred← citeshttps://doi.org/10.1016/j.future.2021.11.008openalex-snapshot

CIMAR, NIMAR, and LMMA: Novel algorithms for thread and memory migrations in user space on NUMA systems using hardware counters

inferred← citeshttps://doi.org/10.1016/j.jss.2016.11.001openalex-snapshot

Nosv: A lightweight nested-virtualization VMM for hosting high performance computing on cloud

inferred← citeshttps://doi.org/10.1109/access.2021.3069991openalex-snapshot

A Performance-Stable NUMA Management Scheme for Linux-Based HPC Systems

inferred← citeshttps://doi.org/10.1109/ds-rt50469.2020.9213639openalex-snapshot

NUMA-Aware Non-Blocking Calendar Queue

inferred← citeshttps://doi.org/10.1109/hpcsim.2016.7568314openalex-snapshot

CPU-core frequency scaling for efficient thread scheduling in transactional memories

inferred← citeshttps://doi.org/10.1109/icrteect67512.2025.11448647openalex-snapshot

Server Memory bandwidth analysis and optimization in Sub-NUMA Clustering mode

inferred← citeshttps://doi.org/10.1109/mascots.2016.69openalex-snapshot

Configurable and Efficient Memory Access Tracing via Selective Expression-Based x86 Binary Instrumentation

inferred← citeshttps://doi.org/10.1109/tc.2022.3222084openalex-snapshot

On the Effects of Transaction Data Access Patterns on Performance in Lock-Based Concurrency Control

inferred← citeshttps://doi.org/10.1145/2975587openalex-snapshot

Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures

inferred← citeshttps://doi.org/10.1145/3006385openalex-snapshot

Affinity-Based Thread and Data Mapping in Shared Memory Systems

inferred← citeshttps://doi.org/10.1145/3127024.3127038openalex-snapshot

Improving the memory access locality of hybrid MPI applications

inferred← citeshttps://doi.org/10.1145/3575693.3575745openalex-snapshot

NUBA: Non-Uniform Bandwidth GPUs

inferred← citeshttps://doi.org/10.3390/app11146486openalex-snapshot

Thread-Aware Mechanism to Enhance Inter-Node Load Balancing for Multithreaded Applications on NUMA Systems

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