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Scheduling of conditional process graphs for the synthesis of embedded systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4757-5388-2openalex-snapshot
Hardware-Software Co-Synthesis of Distributed Embedded Systems
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A co-synthesis approach to embedded system design automation
inferredcites →https://doi.org/10.1007/bf00288685openalex-snapshot
Optimal scheduling for two-processor systems
inferredcites →https://doi.org/10.1016/0743-7315(92)90017-hopenalex-snapshot
SOS: Synthesis of application-specific heterogeneous multiprocessor systems
inferredcites →https://doi.org/10.1016/s0022-0000(75)80008-0openalex-snapshot
NP-complete scheduling problems
inferredcites →https://doi.org/10.1023/a:1008857008151openalex-snapshot
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
inferredcites →https://doi.org/10.1109/71.503776openalex-snapshot
Dynamic critical-path scheduling: an effective technique for allocating task graphs to multiprocessors
inferredcites →https://doi.org/10.1109/dac.1995.249992openalex-snapshot
Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems
inferredcites →https://doi.org/10.1109/isss.1997.621675openalex-snapshot
Embedded system synthesis by timing constraints solving
inferredcites →https://doi.org/10.1109/tc.1984.1676376openalex-snapshot
Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing
inferredcites →https://doi.org/10.1145/217474.217570openalex-snapshot
Performance analysis of embedded software using implicit path enumeration
inferredcites →https://doi.org/10.1145/240518.240633openalex-snapshot
Efficient software performance estimation methods for hardware/software codesign
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.2139/ssrn.4529549openalex-extracted
Green Computing: A Novel Approach for Scheduling Pctgs on Mpsocs
inferred← citeshttps://doi.org/10.1007/0-306-48734-9_17openalex-snapshot
Automatic Generation of Scheduled SystemC Models of Embedded Systems from Extended Task Graphs
inferred← citeshttps://doi.org/10.1007/0-387-26151-6_17openalex-snapshot
Systemc Models for Realistic Simulations Involving Real-Time Operating System Services
inferred← citeshttps://doi.org/10.1007/11564751_11openalex-snapshot
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation
inferred← citeshttps://doi.org/10.1007/3-540-44572-2_4openalex-snapshot
Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform
inferred← citeshttps://doi.org/10.1007/978-1-4419-6345-1_26openalex-snapshot
Intermediate Representations for Simulation and Implementation
inferred← citeshttps://doi.org/10.1007/978-1-4419-6400-7_8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-1-4419-8153-0_3openalex-snapshot
Principles of Design Space Exploration
inferred← citeshttps://doi.org/10.1007/978-3-319-06317-1_9openalex-snapshot
Combining Analytical and Simulation-Based Design Space Exploration for Efficient Time-Critical and Mixed-Criticality Systems
inferred← citeshttps://doi.org/10.1007/978-3-540-85958-1_2openalex-snapshot
A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine
inferred← citeshttps://doi.org/10.1007/978-3-642-16767-6_2openalex-snapshot
A Flexible Hierarchical Approach for Controlling the System-Level Design Complexity of Embedded Systems
inferred← citeshttps://doi.org/10.1007/s10766-007-0032-7openalex-snapshot
A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness
inferred← citeshttps://doi.org/10.1007/s10951-010-0184-yopenalex-snapshot
Stochastic allocation and scheduling for conditional task graphs in multi-processor systems-on-chip
inferred← citeshttps://doi.org/10.1016/j.eswa.2013.09.018openalex-snapshot
Pre-run-time scheduling in real-time systems: Current researches and Artificial Intelligence perspectives
inferred← citeshttps://doi.org/10.1016/j.ifacol.2015.07.016openalex-snapshot
Assignment of unexpected tasks in embedded system design process
inferred← citeshttps://doi.org/10.1016/s1383-7621(00)00048-5openalex-snapshot
Constraints-driven design space exploration for distributed embedded systems
inferred← citeshttps://doi.org/10.1016/s1383-7621(03)00096-1openalex-snapshot
Modeling and formal verification of embedded systems based on a Petri net representation
inferred← citeshttps://doi.org/10.1023/a:1008191425265openalex-snapshot
High-Level Embedded System Specifications Based on Process Activation Conditions
inferred← citeshttps://doi.org/10.1049/ip-cdt:20030837openalex-snapshot
Scheduling and mapping of conditional task graph for the synthesis of low power embedded systems
inferred← citeshttps://doi.org/10.1109/54.679207openalex-snapshot
Codesign of embedded systems: status and trends
inferred← citeshttps://doi.org/10.1109/92.894152openalex-snapshot
Scheduling with bus access optimization for distributed embedded systems
inferred← citeshttps://doi.org/10.1109/92.931229openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/access.2024.3403418openalex-snapshot
Energy-Aware Successor Tree Consistent EDF Scheduling for PCTGs on MPSoCs
inferred← citeshttps://doi.org/10.1109/asap.2000.862404openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/cac.2015.7382674openalex-snapshot
A real-time task scheduling algorithm for multicore embedded systems
inferred← citeshttps://doi.org/10.1109/cit.2006.159openalex-snapshot
Real-Time Scheduling Algorithm Based on Set Division of Resource for Embedded Operating System
inferred← citeshttps://doi.org/10.1109/cjece.2005.1541732openalex-snapshot
Design of embedded compute-intensive processing elements and their scheduling in a reconfigurable environment
inferred← citeshttps://doi.org/10.1109/codes.2002.1003606openalex-snapshot
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems
inferred← citeshttps://doi.org/10.1109/dac.2002.1012699openalex-snapshot
Schedulability of event-driven code blocks in real-time embedded systems
inferred← citeshttps://doi.org/10.1109/dac.2003.1219044openalex-snapshot
Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals
inferred← citeshttps://doi.org/10.1109/date.1999.761224openalex-snapshot
Integrated resource assignment and scheduling of task graphs using finite domain constraints
inferred← citeshttps://doi.org/10.1109/date.2001.915088openalex-snapshot
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
inferred← citeshttps://doi.org/10.1109/date.2003.1253592openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/date.2005.10openalex-snapshot
A Dependability-Driven System-Level Design Approach for Embedded Systems
inferred← citeshttps://doi.org/10.1109/date.2008.4484751openalex-snapshot
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload
inferred← citeshttps://doi.org/10.1109/dsd.2003.1231900openalex-snapshot
Scheduling and assignment for real-time embedded systems with resource contention
inferred← citeshttps://doi.org/10.1109/dsd.2003.1231906openalex-snapshot
A constructive algorithm with look-ahead for mapping and scheduling of task graphs with conditional edges
inferred← citeshttps://doi.org/10.1109/dsd.2003.1231924openalex-snapshot
A novel specification model for IP-based design
inferred← citeshttps://doi.org/10.1109/ecbs.2005.52openalex-snapshot
MoDeII: Modeling and Analyzing Time-Constraints
inferred← citeshttps://doi.org/10.1109/emrts.2000.854008openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/eurmic.1999.793133openalex-snapshot
Synthesis of distributed embedded systems
inferred← citeshttps://doi.org/10.1109/eurmic.1999.794484openalex-snapshot
Low-energy directed architecture selection and task scheduling for system-level design
inferred← citeshttps://doi.org/10.1109/eurmic.1999.794485openalex-snapshot
An improved scheduling technique for time-triggered embedded systems
inferred← citeshttps://doi.org/10.1109/hsc.1999.777428openalex-snapshot
Scheduling with optimized communication for time-triggered embedded systems
inferred← citeshttps://doi.org/10.1109/ibcast.2016.7429886openalex-snapshot
Genetic algorithm for designing reliable embedded system using IP-Cores not resilient to soft-error
inferred← citeshttps://doi.org/10.1109/icasic.2001.982515openalex-snapshot
ASICosyn: co-synthesis of conditional task graphs with custom ASICs
inferred← citeshttps://doi.org/10.1109/iccad.1999.810711openalex-snapshot
FunState-an internal design representation for codesign
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753289openalex-snapshot
Energy-aware scheduling of conditional task graphs with deadlines on MPSoCs
inferred← citeshttps://doi.org/10.1109/icpads.2004.1316111openalex-snapshot
Resource estimation and task scheduling for multithreaded reconfigurable architectures
inferred← citeshttps://doi.org/10.1109/icppw.2000.869150openalex-snapshot
Task concurrency management experiment for power-efficient speed-up of embedded MPEG4 IM1 player
inferred← citeshttps://doi.org/10.1109/iscas.2007.378590openalex-snapshot
Profile-Based Low Power Scheduling for Conditional Task Graph: A Communication Aware Approach
inferred← citeshttps://doi.org/10.1109/issoc.2006.321997openalex-snapshot
A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs
inferred← citeshttps://doi.org/10.1109/isss.1999.814257openalex-snapshot
Path-based edge activation for dynamic run-time scheduling
inferred← citeshttps://doi.org/10.1109/iwv.1998.667134openalex-snapshot
Cyclic process nets as a high-level behavioral specification model for embedded systems synthesis
inferred← citeshttps://doi.org/10.1109/iwv.2000.844535openalex-snapshot
Specification and validation of information processing systems by process encapsulation and symbolic execution
inferred← citeshttps://doi.org/10.1109/lpe.2003.1231938openalex-snapshot
Power-aware scheduling of conditional task graphs in real-time multiprocessor systems
inferred← citeshttps://doi.org/10.1109/pdp.2006.65openalex-snapshot
Scheduling programs with conditional branches for look-ahead dynamically reconfigurable systems
inferred← citeshttps://doi.org/10.1109/rtas.2008.9openalex-snapshot
Schedulability Analysis of MSC-based System Models
inferred← citeshttps://doi.org/10.1109/rtcsa.1999.811257openalex-snapshot
Schedulability-driven communication synthesis for time triggered embedded systems
inferred← citeshttps://doi.org/10.1109/samos.2013.6621123openalex-snapshot
Dynamic task mapping onto multi-core architectures through stream rewriting
inferred← citeshttps://doi.org/10.1109/tcad.2009.2013536openalex-snapshot
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms
inferred← citeshttps://doi.org/10.1109/tmscs.2018.2854787openalex-snapshot
Hardware Accelerated Mappers for Hadoop MapReduce Streaming
inferred← citeshttps://doi.org/10.1109/tpds.2007.70784openalex-snapshot
Hybrid Scheduling of Dynamic Task Graphs with Selective Duplication for Multiprocessors under Memory and Time Constraints
inferred← citeshttps://doi.org/10.1109/tvlsi.2007.893660openalex-snapshot
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems
inferred← citeshttps://doi.org/10.1109/vlsisoc.2007.4402503openalex-snapshot
Power optimization for conditional task graphs in DVS enabled multiprocessor systems
inferred← citeshttps://doi.org/10.1145/1403375.1403644openalex-snapshot
Synthesis of fault-tolerant embedded systems
inferred← citeshttps://doi.org/10.1145/288548.288560openalex-snapshot
Representation of process mode correlation for scheduling
inferred← citeshttps://doi.org/10.1524/itit.46.2.59.29082openalex-snapshot
Konzepte zur Beherrschung der Entwurfskomplexität eingebetteter Systeme (Concepts for the Control of the Complexity of Embedded System Design)
inferred← citeshttps://doi.org/10.24251/hicss.2018.715openalex-snapshot
Energy-Aware Scheduling of Conditional Task Graphs on NoC-Based MPSoCs
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