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Optimization of Regular Expression Pattern Matching Circuits on FPGA
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/dac.2005.193807openalex-snapshot
A pattern matching co-processor for network security
inferredcites →https://doi.org/10.1109/fccm.2001.22openalex-snapshot
Fast Regular Expression Matching Using FPGAs
inferredcites →https://doi.org/10.1109/fpga.2002.1106666openalex-snapshot
Assisting network intrusion detection with reconfigurable hardware
inferredcites →https://doi.org/10.1109/fpga.2003.1227239openalex-snapshot
Implementation of a content-scanning module for an Internet firewall
inferredcites →https://doi.org/10.1145/1055626.1055640openalex-snapshot
Configurable string matching hardware for speeding up intrusion detection
inferredcites →https://doi.org/10.1145/1065579.1065641openalex-snapshot
A pattern matching coprocessor for network security
inferredcites →https://doi.org/10.1145/968280.968312openalex-snapshot
Time and area efficient pattern matching on FPGAs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-540-71431-6_17openalex-snapshot
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues
inferred← citeshttps://doi.org/10.1007/978-3-540-78610-8_8openalex-snapshot
Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-642-00641-8_32openalex-snapshot
Regular Expression Pattern Matching Supporting Constrained Repetitions
inferred← citeshttps://doi.org/10.1007/978-3-642-19475-7_4openalex-snapshot
A Regular Expression Matching Circuit Based on a Decomposed Automaton
inferred← citeshttps://doi.org/10.1007/978-3-642-55224-3_51openalex-snapshot
The Regular Expression Matching Algorithm for the Energy Efficient Reconfigurable SoC
inferred← citeshttps://doi.org/10.1007/s11265-007-0131-0openalex-snapshot
Regular Expression Matching in Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1016/j.comcom.2011.12.009openalex-snapshot
String alignment pre-detection using unique subsequences for FPGA-based network intrusion detection
inferred← citeshttps://doi.org/10.1016/j.jnca.2012.07.010openalex-snapshot
Deep packet inspection tools and techniques in commodity platforms: Challenges and trends
inferred← citeshttps://doi.org/10.1016/j.micpro.2012.04.004openalex-snapshot
A pipelined processor architecture for regular expression string matching
inferred← citeshttps://doi.org/10.1016/j.micpro.2012.05.009openalex-snapshot
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition
inferred← citeshttps://doi.org/10.1016/j.sysarc.2013.03.013openalex-snapshot
ENREM: An efficient NFA-based regular expression matching engine on reconfigurable hardware for NIDS
inferred← citeshttps://doi.org/10.1080/00207210801924107openalex-snapshot
Synthesis of regular expressions for FPGAs
inferred← citeshttps://doi.org/10.1080/00207217.2014.938313openalex-snapshot
FPGA-accelerated algorithm for the regular expression matching system
inferred← citeshttps://doi.org/10.1109/ddecs.2011.5783121openalex-snapshot
Reduction of FPGA resources for regular expression matching by relation similarity
inferred← citeshttps://doi.org/10.1109/euc.2014.52openalex-snapshot
On How to Efficiently Implement Regular Expression Matching on FPGA-Based Systems
inferred← citeshttps://doi.org/10.1109/fpl.2010.20openalex-snapshot
A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching
inferred← citeshttps://doi.org/10.1109/fpl.2010.21openalex-snapshot
Automation Framework for Large-Scale Regular Expression Matching on FPGA
inferred← citeshttps://doi.org/10.1109/fpt.2006.270302openalex-snapshot
Regular expression matching for reconfigurable packet inspection
inferred← citeshttps://doi.org/10.1109/fpt.2009.5377632openalex-snapshot
Automated dynamic reconfiguration for high-performance regular expression searching
inferred← citeshttps://doi.org/10.1109/glocomw.2011.6162539openalex-snapshot
Characterizing signature sets for testing DPI systems
inferred← citeshttps://doi.org/10.1109/greencom.2011.39openalex-snapshot
PeRex: A Power Efficient FPGA-based Architecture for Regular Expression Matching
inferred← citeshttps://doi.org/10.1109/hoti.2008.14openalex-snapshot
Constraint Repetition Inspection for Regular Expression on FPGA
inferred← citeshttps://doi.org/10.1109/icc.2009.5198928openalex-snapshot
Distributed Intrusion Detection with Intelligent Network Interfaces for Future Networks
inferred← citeshttps://doi.org/10.1109/icdcs.2016.63openalex-snapshot
A De-compositional Approach to Regular Expression Matching for Network Security Applications
inferred← citeshttps://doi.org/10.1109/icnc.2011.23openalex-snapshot
Optimization of Regular Expression Processing Circuits for NIDS on FPGA
inferred← citeshttps://doi.org/10.1109/icnp.2013.6733572openalex-snapshot
A few bits are enough - ASIC friendly Regular Expression matching for high speed network security systems
inferred← citeshttps://doi.org/10.1109/infcom.2011.5934986openalex-snapshot
Space-time tradeoff in regular expression matching with semi-deterministic finite automata
inferred← citeshttps://doi.org/10.1109/pact.2011.73openalex-snapshot
Optimizing Regular Expression Matching with SR-NFA on Multi-Core Systems
inferred← citeshttps://doi.org/10.1109/tc.2011.129openalex-snapshot
High-Performance and Compact Architecture for Regular Expression Matching on FPGA
inferred← citeshttps://doi.org/10.1109/tnet.2019.2941920openalex-snapshot
A De-Compositional Approach to Regular Expression Matching for Network Security
inferred← citeshttps://doi.org/10.1109/tpds.2012.116openalex-snapshot
MIN-MAX: A Counter-Based Algorithm for Regular Expression Matching
inferred← citeshttps://doi.org/10.1109/vlsisoc.2007.4402466openalex-snapshot
ReCPU: A parallel and pipelined architecture for regular expression matching
inferred← citeshttps://doi.org/10.1145/1323548.1323571openalex-snapshot
Compiling PCRE to FPGA for accelerating SNORT IDS
inferred← citeshttps://doi.org/10.1145/1403375.1403681openalex-snapshot
An adaptable FPGA-based system for regular expression matching
inferred← citeshttps://doi.org/10.1145/1477942.1477948openalex-snapshot
Compact architecture for high-throughput regular expression matching on FPGA
inferred← citeshttps://doi.org/10.1145/1575779.1575783openalex-snapshot
Space Optimization on Counters for FPGA-Based Perl Compatible Regular Expressions
inferred← citeshttps://doi.org/10.1145/1723112.1723149openalex-snapshot
A modular NFA architecture for regular expression matching
inferred← citeshttps://doi.org/10.1145/2939379openalex-snapshot
A Flexible SoC and Its Methodology for Parser-Based Applications
inferred← citeshttps://doi.org/10.1155/2009/301512openalex-snapshot
Software Toolchain for Large‐Scale RE‐NFA Construction on FPGA
inferred← citeshttps://doi.org/10.1186/1471-2105-9-197openalex-snapshot
Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research
inferred← citeshttps://doi.org/10.1201/b13055-7openalex-snapshot
Large-Scale Regular Expression Matching on FPGA
inferred← citeshttps://doi.org/10.1587/transinf.e95.d.364openalex-snapshot
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton
inferred← citeshttps://doi.org/10.3115/v1/p15-2063openalex-snapshot
Language Identification and Modeling in Specialized Hardware
inferred← citeshttps://doi.org/10.4018/978-1-4666-2050-6.ch016openalex-snapshot
Wild-Inspired Intrusion Detection System Framework for High Speed Networks (f|p) IDS Framework
inferred← citeshttps://doi.org/10.4018/jisp.2011100104openalex-snapshot
Wild-Inspired Intrusion Detection System Framework for High Speed Networks (f|p) IDS Framework
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amm.556-562.1730openalex-snapshot
Regular Expression Matching Algorithm Based on FPGA Circuit
inferred← citeshttps://doi.org/10.48550/arxiv.0909.1781openalex-snapshot
Boosting XML Filtering with a Scalable FPGA-based Architecture
inferred← citeshttps://doi.org/10.5121/csit.2015.51200openalex-snapshot
Computer Science & Information Technology ( CS & IT )
inferred← citeshttps://doi.org/10.5121/csit.2015.51201openalex-snapshot
Efficient Failure Processing Architecture in Regular Expression Processor
inferred← citeshttps://doi.org/10.9708/jksci.2011.16.5.013openalex-snapshot
A Hardware Architecture of Regular Expression Pattern Matching for Deep Packet Inspection
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