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Toward a Software Infrastructure for the Cyclops-64 Cellular Architecture
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/ipdps.2004.1302991openalex-snapshot
Fault-aware job scheduling for bBueGene/L systems
inferredcites →https://doi.org/10.1109/ipdps.2005.434openalex-snapshot
TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture
inferredcites →https://doi.org/10.1145/582034.582074openalex-snapshot
Scalable parallel application launch on Cplant™
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-540-68555-5_19openalex-snapshot
Performance Characteristics of OpenMP Language Constructs on a Many-core-on-a-chip Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-03869-3_78openalex-snapshot
Tile Percolation: An OpenMP Tile Aware Parallelization Technique for the Cyclops-64 Multicore Processor
inferred← citeshttps://doi.org/10.1007/978-3-642-13374-9_6openalex-snapshot
TL-DAE: Thread-Level Decoupled Access/Execution for OpenMP on the Cyclops-64 Many-Core Processor
inferred← citeshttps://doi.org/10.1007/978-3-642-19595-2_6openalex-snapshot
Locality Optimization of Stencil Applications Using Data Dependency Graphs
inferred← citeshttps://doi.org/10.1007/978-3-642-36036-7_18openalex-snapshot
Polytasks: A Compressed Task Representation for HPC Runtimes
inferred← citeshttps://doi.org/10.1007/s10766-015-0373-6openalex-snapshot
The Design and Implementation of TIDeFlow: A Dataflow-Inspired Execution Model for Parallel Loops and Task Pipelining
inferred← citeshttps://doi.org/10.1016/j.future.2013.09.029openalex-snapshot
Architecture-based design and optimization of genetic algorithms on multi- and many-core systems
inferred← citeshttps://doi.org/10.1016/j.procs.2011.04.217openalex-snapshot
10x10: A General-purpose Architectural Approach to Heterogeneity and Energy Efficiency
inferred← citeshttps://doi.org/10.1016/j.procs.2015.05.365openalex-snapshot
FreshBreeze: A Data Flow Approach for Meeting DDDAS Challenges
inferred← citeshttps://doi.org/10.1109/array.2010.5613291openalex-snapshot
CABSim: A cycle-accurate array processor simulation environment for digital radio astronomy
inferred← citeshttps://doi.org/10.1109/dfm.2011.11openalex-snapshot
TIDeFlow: The Time Iterated Dependency Flow Execution Model
inferred← citeshttps://doi.org/10.1109/hpec.2018.8547560openalex-snapshot
GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing
inferred← citeshttps://doi.org/10.1109/igcc.2015.7393735openalex-snapshot
Energy efficient multi-level tiling for dense matrix multiplication on many-core architecture
inferred← citeshttps://doi.org/10.1109/ipdps.2006.1639301openalex-snapshot
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
inferred← citeshttps://doi.org/10.1109/ipdps.2006.1639574openalex-snapshot
Hierarchical multithreading: programming model and system software
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370639openalex-snapshot
Optimizing the Fast Fourier Transform on a Multi-core Architecture
inferred← citeshttps://doi.org/10.1109/ispa.2009.22openalex-snapshot
Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor
inferred← citeshttps://doi.org/10.1109/tadvp.2007.909457openalex-snapshot
Analyzing the Value of Using Three-Dimensional Electronics for a High-Performance Computational System
inferred← citeshttps://doi.org/10.1109/tpds.2008.78openalex-snapshot
Improving Performance of Dynamic Programming via Parallelism and Locality on Multicore Architectures
inferred← citeshttps://doi.org/10.1145/1229428.1229459openalex-snapshot
Optimized lock assignment and allocation
inferred← citeshttps://doi.org/10.1145/1248377.1248399openalex-snapshot
A parallel dynamic programming algorithm on a multi-core architecture
inferred← citeshttps://doi.org/10.1145/2086696.2086728openalex-snapshot
Toward high-throughput algorithms on many-core architectures
inferred← citeshttps://doi.org/10.1145/3149704.3149705openalex-snapshot
Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications
inferred← citeshttps://doi.org/10.1145/3418082openalex-snapshot
Toward a Microarchitecture for Efficient Execution of Irregular Applications
inferred← citeshttps://doi.org/10.2172/1028920openalex-snapshot
Summary of multi-core hardware and programming model investigations
inferred← citeshttps://doi.org/10.2172/935031openalex-snapshot
Center for Programming Models for Scalable Parallel Computing: Future Programming Models
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