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Row buffer locality aware caching policies for hybrid memories
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/date.2011.5763155openalex-snapshot
MLP aware heterogeneous memory system
inferredcites →https://doi.org/10.1109/hpca.2010.5416642openalex-snapshot
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/icpp.1996.537156openalex-snapshot
Reducing conflicts in direct-mapped caches with a temporality-based design
inferredcites →https://doi.org/10.1109/imw.2010.5488395openalex-snapshot
Architectural design for next generation heterogeneous memory systems
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/l-ca.2012.2openalex-snapshot
Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management
inferredcites →https://doi.org/10.1109/micro.2004.28openalex-snapshot
Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
inferredcites →https://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferredcites →https://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/mm.2010.102openalex-snapshot
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue
inferredcites →https://doi.org/10.1109/mm.2010.24openalex-snapshot
Phase-Change Technology and the Future of Main Memory
inferredcites →https://doi.org/10.1109/pact.2009.30openalex-snapshot
Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1629575.1629589openalex-snapshot
Better I/O through byte-addressable, persistent memory
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot
Reducing memory interference in multicore systems via application-aware memory channel partitioning
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/224538.224622openalex-snapshot
A data cache with multiple caching strategies tuned to different types of locality
inferredcites →https://doi.org/10.1145/2591635.2667170openalex-snapshot
A data cache with multiple caching strategies tuned to different types of locality
inferredcites →https://doi.org/10.1145/264107.264213openalex-snapshot
Run-time adaptive cache hierarchy management via reference analysis
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1147/rd.462.0187openalex-snapshot
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology
inferredcites →https://doi.org/10.1184/r1/6468701openalex-snapshot
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
inferredcites →https://doi.org/10.5555/314613.314715openalex-snapshot
Flow and stretch metrics for scheduling continuous job streams
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Main Memory Scaling: Challenges and Solution Directions
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Pattern-Aware Staging for Hybrid Memory Systems
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Efficient Management for Hybrid Memory in Managed Language Runtime
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HBM-Resident Prefetching for Heterogeneous Memory System
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The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption
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Emerging and Nonvolatile Memory
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Emerging and Non-volatile Memory
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An OS-level Data Distribution Method in DRAM-PCM Hybrid Memory
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Reliability Issues in Flash-Memory-Based Solid-State Drives: Experimental Analysis, Mitigation, Recovery
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A Modern Primer on Processing in Memory
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Energy-aware assignment and scheduling for hybrid main memory in embedded systems
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Energy minimization in the STT-RAM-based high-capacity last-level caches
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LARA: Locality-aware resource allocation to improve GPU memory-access time
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A Survey of Phase Change Memory Systems
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A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future Directions
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Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing
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A Hybrid Memory Architecture Supporting Fine-Grained Data Migration
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The New Hardware Development Trend and the Challenges in Data Management and Analysis
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Simple Operations in Memory to Reduce Data Movement
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Processing data where it makes sense: Enabling in-memory computation
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Energy-aware page replacement and consistency guarantee for hybrid NVM–DRAM memory systems
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Phase Change Memory lifetime enhancement via online data swapping
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Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
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Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture
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Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System
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Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD
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A 3-Level Cache Miss Model for a Nonvolatile Extension to Transcendent Memory
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Utility-Based Hybrid Memory Management
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Performance Modeling for Optimal Data Placement on GPU with Heterogeneous Memory Systems
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Algorithm-Directed Crash Consistence in Non-volatile Memory for HPC
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MemFlex: A Hybrid Memory System to Boost Cost of Ownership in Data Centers
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Characterizing Application Memory Error Vulnerability to Optimize Datacenter Cost via Heterogeneous-Reliability Memory
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DUANG: Fast and lightweight page migration in asymmetric memory systems
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Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
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ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
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Stealth-Persist: Architectural Support for Persistent Applications in Hybrid Memory Systems
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Sentinel: Efficient Tensor Migration and Allocation on Heterogeneous Memory Systems for Deep Learning
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3D-DRAM Performance for Different OpenMP Scheduling Techniques in Multicore Systems
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Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping
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HAP: Hybrid-memory-Aware Partition in shared Last-Level Cache
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Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory
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Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture
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AdaptHM: A Fully Adaptive Data Migration Strategy for Hybrid Memory Systems
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Hybrid Main Memory for High Bandwidth Multi-Core System
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NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors
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Hierarchical Hybrid Memory Management in OS for Tiered Memory Systems
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APMigration: Improving Performance of Hybrid Memory Performance via An Adaptive Page Migration Method
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Hotspot-Aware Hybrid Memory Management for In-Memory Key-Value Stores
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Infection-Based Dead Page Prediction in Hybrid Memory Architecture
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An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints
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Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories
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Software-managed energy-efficient hybrid DRAM/NVM main memory
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Memory Row Reuse Distance and its Role in Optimizing Application Performance
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Energy-Efficient In-Memory Data Stores on Hybrid Memory Hierarchies
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Memory Row Reuse Distance and its Role in Optimizing Application Performance
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Rethinking Memory System Design (along with Interconnects)
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Rethinking Computer Architectures and Software Systems for Phase-Change Memory
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Understanding Latency Variation in Modern DRAM Chips
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Algorithm-Directed Data Placement in Explicitly Managed Non-Volatile Memory
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Understanding Latency Variation in Modern DRAM Chips
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Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization
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Rethinking memory system design
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Translation-Triggered Prefetching
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Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures
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Translation-Triggered Prefetching
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Translation-Triggered Prefetching
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Translation-Triggered Prefetching
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Analyzing and modeling the impact of memory latency and bandwidth on application performance
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A Case for Granularity Aware Page Migration
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Design guidelines for high-performance SCM hierarchies
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FlatFlash: Exploiting the Byte-Accessibility of SSDs within a Unified Memory-Storage Hierarchy
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Panthera: holistic memory management for big data processing over hybrid memories
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Page migration support for disaggregated non-volatile memories
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Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories
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Improving phase change memory performance with data content aware access
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Block-Granularity-Aware Caching
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PreFAM: Understanding the Impact of Prefetching in Fabric-Attached Memory Architectures
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Brief Announcement: Spatial Locality and Granularity Change in Caching
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Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories
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Efficient Compactions between Storage Tiers with PrismDB
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ECC-Map: A Resilient Wear-Leveled Memory-Device Architecture with Low Mapping Overhead
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NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance
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PCM-2R: Accelerating MLC PCM Writes via Data Reshaping and Remapping
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The Main Memory System: Challenges and Opportunities
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Techniques for Shared Resource Management in Systems with Throughput Processors
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Main memory controller with multiple media technologies for big data workloads
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A Study on Flat-Address-Space Heterogeneous Memory Architectures
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Migration mechanism of heterogeneous memory pages using a two-way Hash chain list
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A Survey on Phase Change Memory-Aware Cache Management
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Research Problems and Opportunities in Memory Systems
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A survey of power management techniques for phase change memory
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Optimized fast data migration for hybrid DRAM/STT-MRAM main memory
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The RowHammer problem and other issues we may face as memory becomes denser
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Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss
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HME: A lightweight emulator for hybrid memory
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UIMigrate: Adaptive Data Migration for Hybrid Non-Volatile Memory Systems
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Intelligent Architectures for Intelligent Computing Systems
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Transformer: An OS-Supported Reconfigurable Hybrid Memory Architecture
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Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System
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Photonics opportunities in modern computing systems
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Energy Saving Techniques for Phase Change Memory (PCM)
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Managing Hybrid Main Memories with a Page-Utility Driven Performance Model
inferred← citeshttps://doi.org/10.48550/arxiv.1601.06903openalex-snapshot
Tiered-Latency DRAM (TL-DRAM)
inferred← citeshttps://doi.org/10.48550/arxiv.1609.02067openalex-snapshot
Practical Data Compression for Modern Memory Hierarchies
inferred← citeshttps://doi.org/10.48550/arxiv.1703.07725openalex-snapshot
Memos: Revisiting Hybrid Memory Management in Modern Operating System
inferred← citeshttps://doi.org/10.48550/arxiv.1704.02677openalex-snapshot
Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation
inferred← citeshttps://doi.org/10.48550/arxiv.1711.11427openalex-snapshot
Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery
inferred← citeshttps://doi.org/10.48550/arxiv.1802.00320openalex-snapshot
Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions
inferred← citeshttps://doi.org/10.48550/arxiv.1808.04016openalex-snapshot
Architectural Techniques for Improving NAND Flash Memory Reliability
inferred← citeshttps://doi.org/10.48550/arxiv.1903.03988openalex-snapshot
Processing Data Where It Makes Sense: Enabling In-Memory Computation
inferred← citeshttps://doi.org/10.48550/arxiv.1909.05182openalex-snapshot
Sentinel: Runtime Data Management on Heterogeneous Main MemorySystems for Deep Learning
inferred← citeshttps://doi.org/10.48550/arxiv.2105.03814openalex-snapshot
Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture
inferred← citeshttps://doi.org/10.48550/arxiv.2111.02325openalex-snapshot
Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study
inferred← citeshttps://doi.org/10.6688/jise.2015.31.5.8openalex-snapshot
Exploiting Page Write Pattern for Power Management of Hybrid DRAM/PRAM Memory System.
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