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VerMI: Verification Tool for Masked Implementations

https://doi.org/10.1109/icecs.2018.8617841
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/11935308_38openalex-snapshot
Threshold Implementations Against Side-Channel Attacks and Glitches
inferredcites →https://doi.org/10.1007/978-0-387-38162-6openalex-snapshot
Power Analysis Attacks: Revealing the Secrets of Smart Cards
inferredcites →https://doi.org/10.1007/978-3-319-08302-5_13openalex-snapshot
Efficient and First-Order DPA Resistant Implementations of Keccak
inferredcites →https://doi.org/10.1007/978-3-319-49445-6_21openalex-snapshot
A Methodology for the Characterisation of Leakages in Combinatorial Logic
inferredcites →https://doi.org/10.1007/978-3-319-52153-4_6openalex-snapshot
An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order
inferredcites →https://doi.org/10.1007/978-3-319-66787-4_7openalex-snapshot
Changing of the Guards: A Simple and Efficient Method for Achieving Uniformity in Threshold Sharing
inferredcites →https://doi.org/10.1007/978-3-319-78375-8_11openalex-snapshot
Formal Verification of Masked Hardware Implementations in the Presence of Glitches
inferredcites →https://doi.org/10.1007/978-3-319-93387-0_4openalex-snapshot
Formal Verification of Side-Channel Countermeasures via Elementary Circuit Transformations
inferredcites →https://doi.org/10.1007/978-3-540-45146-4_27openalex-snapshot
Private Circuits: Securing Hardware against Probing Attacks
inferredcites →https://doi.org/10.1007/978-3-642-40349-1_17openalex-snapshot
Sleuth: Automated Verification of Software Power Analysis Countermeasures
inferredcites →https://doi.org/10.1007/978-3-662-45608-8_18openalex-snapshot
Higher-Order Threshold Implementations
inferredcites →https://doi.org/10.1007/978-3-662-46800-5_18openalex-snapshot
Verified Proofs of Higher-Order Masking
inferredcites →https://doi.org/10.1007/978-3-662-47989-6_37openalex-snapshot
Consolidating Masking Schemes
inferredcites →https://doi.org/10.1007/978-3-662-52993-5_11openalex-snapshot
Detecting Flawed Masking Schemes with Leakage Detection Tests
inferredcites →https://doi.org/10.1109/dsd.2017.21openalex-snapshot
Higher-Order Side-Channel Protected Implementations of KECCAK
inferredcites →https://doi.org/10.1145/2996366.2996428openalex-snapshot
Masking AES With d+1 Shares in Hardware
inferredcites →https://doi.org/10.46586/tches.v2018.i1.269-290openalex-snapshot
Rhythmic Keccak: SCA Security and Low Latency in HW

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-16350-1_15openalex-snapshot
Shuffle and Mix: On the Diffusion of Randomness in Threshold Implementations of Keccak
inferred← citeshttps://doi.org/10.1007/978-3-030-88885-5_17openalex-snapshot
Proving SIFA Protection of Masked Redundant Circuits
inferred← citeshttps://doi.org/10.1007/978-3-031-91101-9_2openalex-snapshot
INDIANA - Verifying (Random) Probing Security Through Indistinguishability Analysis
inferred← citeshttps://doi.org/10.1007/978-3-319-96142-2_12openalex-snapshot
SCInfer: Refinement-Based Verification of Software Countermeasures Against Side-Channel Attacks
inferred← citeshttps://doi.org/10.1007/s11334-022-00448-4openalex-snapshot
Proving SIFA protection of masked redundant circuits
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00056openalex-snapshot
Scripting the Unpredictable: Automate Fault Injection in RTL Simulation for Vulnerability Assessment
inferred← citeshttps://doi.org/10.1109/host45689.2020.9300264openalex-snapshot
Cryptographic Fault Diagnosis using VerFI
inferred← citeshttps://doi.org/10.1109/host68814.2026.11604894openalex-snapshot
Efficient Low-Latency Masking of Ascon Without Fresh Randomness
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00029openalex-snapshot
Real-World Snapshots vs. Theory: Questioning the t-Probing Security Model
inferred← citeshttps://doi.org/10.1109/tc.2020.3022979openalex-snapshot
Hardware Private Circuits: From Trivial Composition to Full Verification
inferred← citeshttps://doi.org/10.1109/tifs.2021.3123527openalex-snapshot
LLTI: Low-Latency Threshold Implementations
inferred← citeshttps://doi.org/10.1145/3428015openalex-snapshot
A Hybrid Approach to Formal Verification of Higher-Order Masked Arithmetic Programs
inferred← citeshttps://doi.org/10.1145/3576199openalex-snapshot
Challenges and Opportunities of Security-Aware EDA
inferred← citeshttps://doi.org/10.23919/date64628.2025.10993221openalex-snapshot
One More Motivation to Use Evaluation Tools This Time for Hardware Multiplicative Masking of AES
inferred← citeshttps://doi.org/10.31224/osf.io/d48k6openalex-snapshot
fmdtools: A Fault Propagation Toolkit for Resilience Assessment in Early Design
inferred← citeshttps://doi.org/10.36001/ijphm.2021.v12i3.2954openalex-snapshot
Fmdtools
inferred← citeshttps://doi.org/10.46586/tches.v2018.i3.431-468openalex-snapshot
Multiplicative Masking for AES in Hardware
inferred← citeshttps://doi.org/10.46586/tches.v2018.i3.596-626openalex-snapshot
Spin Me Right Round Rotational Symmetry for FPGA-Specific AES
inferred← citeshttps://doi.org/10.46586/tches.v2019.i3.119-147openalex-snapshot
Consolidating Security Notions in Hardware Masking
inferred← citeshttps://doi.org/10.46586/tches.v2022.i4.255-284openalex-snapshot
VERICA - Verification of Combined Attacks
inferred← citeshttps://doi.org/10.46586/tches.v2024.i1.229-263openalex-snapshot
StaTI: Protecting against Fault Attacks Using Stable Threshold Implementations
inferred← citeshttps://doi.org/10.46586/tches.v2024.i1.433-456openalex-snapshot
Quantile: Quantifying Information Leakage
inferred← citeshttps://doi.org/10.48550/arxiv.2106.12714openalex-snapshot
Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners
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