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The memory of bandwidth bottleneck and its amelioration by a compiler
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-57502-2_53openalex-snapshot
Collective loop fusion for array contraction
inferredcites →https://doi.org/10.1016/0743-7315(88)90002-0openalex-snapshot
Estimating interlock and improving balance for pipelined architectures
inferredcites →https://doi.org/10.1145/109025.109077openalex-snapshot
Optimization of array accesses by collective loop transformations
inferredcites →https://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferredcites →https://doi.org/10.1145/237090.237163openalex-snapshot
The intrinsic bandwidth requirements of ordinary programs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Improving the Memory Bandwidth Utilization Using Loop Transformations
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Instruction Balance and Its Relation to Program Energy Consumption
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Compile Time Modeling of Off-Chip Memory Bandwidth for Parallel Loops
inferred← citeshttps://doi.org/10.1007/978-3-540-30102-8_18openalex-snapshot
Impact of Register-Cache Bandwidth Variation on Processor Performance
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Generalized Index-Set Splitting
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A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing
inferred← citeshttps://doi.org/10.1007/978-3-642-35632-2_8openalex-snapshot
Detecting Unread Memory Using Dynamic Binary Translation
inferred← citeshttps://doi.org/10.1016/j.jpdc.2003.09.005openalex-snapshot
Improving effective bandwidth through compiler enhancement of global cache reuse
inferred← citeshttps://doi.org/10.1016/s1383-7621(02)00122-4openalex-snapshot
Increasing hardware data prefetching performance using the second-level cache
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Avoiding Store Misses to Fully Modified Cache Blocks
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Development of In-Memory Computing Device Using Positive Feedback Field Effect Transistor Based on NAND Flash Array
inferred← citeshttps://doi.org/10.1109/aina.2015.175openalex-snapshot
A Thread Merging Transformation to Improve Throughput of Multiple Programs
inferred← citeshttps://doi.org/10.1109/csd.2001.981763openalex-snapshot
Analysis of performance limitations in multithreaded multiprocessor architectures
inferred← citeshttps://doi.org/10.1109/estmed.2004.1359707openalex-snapshot
Data assignment and access scheduling exploration for multi-layer memory architectures
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Using scratchpad to exploit object locality in Java
inferred← citeshttps://doi.org/10.1109/ipdps.2001.924975openalex-snapshot
Improving effective bandwidth through compiler enhancement of global cache reuse
inferred← citeshttps://doi.org/10.1109/ispass.2004.1291361openalex-snapshot
Effectiveness of simple memory models for performance prediction
inferred← citeshttps://doi.org/10.1109/tpds.2007.1026openalex-snapshot
Analyzing the Energy-Time Trade-Off in High-Performance Computing Applications
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A tuning framework for software-managed memory hierarchies
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Static reuse distances for locality-based optimizations in MATLAB
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A coldness metric for cache optimization
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On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches
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A Case For Intra-rack Resource Disaggregation in HPC
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Data and memory optimization techniques for embedded systems
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Language support for Morton-order matrices
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Two techniques for reconciling algorithm parallelism with memory constraints
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Data remapping for design space optimization of embedded memory systems
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Contention Aware Scheduler with Accurate Memory Bandwidth Measurement for Predictable Multicore Software
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Performance analysis and optimization of the Java memory system
inferred← citeshttps://doi.org/10.48550/arxiv.1412.0544openalex-snapshot
Optimizing Large-Scale ODE Simulations
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Analysis of performance bottlenecks in multithreaded multiprocessor systems
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